This document discusses challenges with collaboration and reuse in mixed-signal design verification. It notes that using incompatible tools for modeling at different design levels delays verification. It suggests that using analog/mixed-signal simulators with common modeling languages and virtual labs with standardized devices and behaviors could improve collaboration, reuse of test cases, and speed up the verification process.

1. Reuse and Collaboration Opportunities in AMS
Design and Verification
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2. Overview
Mixed-signal simulators for architectural design improve
collaboration, reuse, and the verification schedule
Standards or models can improve verification and
validation collaboration and reuse
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3. Who Legerity is and What We Do
Carrier Telephony
• High voltage mixed-signal telephone
drivers for central offices, local
neighborhood boxes, and analog PBXs
Consumer Telephony
• Voice-enabled cable modems, voice-
enabled DSL modems, analog terminal
adapters
• Phone ready PCs
• Voice over wireless LAN
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4. Modeling and Design Tool Incompatability
SYSTEM ARCHITECTURE
Matlab/Simulink
Software Mechanical
SDK VHDL-AMS, FEA
C Digital
Logic Simulator
Analog
Spice P hysics
R TL A nalog
VERIFICATION
Imagine verification is a fan...
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5. Incompatible Models Delay Verification
SYSTEM
SYSTEM
ARCHITECTURE
ARCHITECTURE
MICRO
MICRO
ARCHITECTURE
ARCHITECTURE
MODELING
MODELING
VERIFICATION
VERIFICATION
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6. Analog-Mixed-Signal Simulators Provide Solution
SYSTEM ARCHITECTURE
Analog/Mixed-signal
Software Mechanical
SystemC VHDL-AMS
Digital Analog
Logic Simulator Spice
VERIFICATION
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7. Common Tools Move Verification Forward
SYSTEM
SYSTEM
ARCHITECTURE
ARCHITECTURE
MICRO
MICRO
ARCHITECTURE
ARCHITECTURE
MODELING
MODELING
VERIFICATION
VERIFICATION
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8. Very Little Test Case Sharing – As Expensive As
Design
SYSTEM ARCHITECTURE SYSTEM TEST CASES
Software Mechanical
DESIGN TEST CASES
Digital Analog
VERIFICATION TEST CASES
VERIFICATION
RANDOM TESTCASE GEN
HARDWARE VALIDATION VALIDATION TEST CASES
PRODUCT TEST PRODUCTION TEST CASES
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9. Virtual Lab Or Standard Devices/Languages May
Provide Solution
SD
1 2 3 4 5 6 7 8 9 10 11 12
SD
P R O L IA N T
8000
ESC
SD
DLT
Hardware vendors provide simulation models of their devices
Define a standard set of devices and behavior
A standard mixed-signal verification assertion language can be defined
Bonus: Common environment allows common GUI between laboratory and
simulation (e.g. LabView)
Question: Do similar issues arise in signal processing and mechanical designs?
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10. Summary
Problems
• Collaboration between architecture and implementation
• Delayed verification
• Little test case, test bench, or RTG infrastructure reuse
Solutions
• Common design and modeling simulation tools
• Virtual lab or language standards
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