Maxim Zaporozchenko has over 10 years of experience in ASIC/FPGA design including backend design from synthesis through layout. He has a BSc in electrical engineering from Tel Aviv University and is currently pursuing an MBA. His experience includes projects in 28nm design at Marvell and an ASIC communication controller design during his studies. He is proficient in Verilog, VHDL, C, and backend tools from Magma, Synopsys, and Altera.

1. Maxim Zaporozchenko
Cell : 054-5325201 | E-mail : maximzap@gmail.com
ASIC/FPGA Designer
PROFESSIONAL EXPERIENCE
2011 - now Back End engineer, “Marvell”
 Experience in full Backend flow From Synthesis through P&R and static timing environment
build and verification as well as physical DRC/LVS verification concluded by approved
tapeout quality layout.
 Experience with Static timing analysis- Synopsis (PrimeTime) ,LVS/DRC – Caliber ,TCL
programming
 Technology: 28nm
 Backend tools: Magma (Talus), Prime Time, Calibre.
2011 ASIC Design Program, “Chip Design College”
ASIC Chip Level Design :
 Architecture definition, ASIC Top-Level Spec and Verification Spec creation, IP blocks.
 Integration: Analog and Digital IPs, Memories, Pads.
Automatic Verification Environment: Synthesis and STA ( by Synopsys DC-Compiler ), RTL
Design and Verification ( Functional & GLS ) by VerilogHDL on ModelSim
ASIC Project (based Synopsys Front-End flow): Communication Controller Design.
Includes CPU Bus IF, Control unit, Clock & Reset controllers, Test Controller,
Digital & Analog IPs (POR, DPRAM, UART core, Pads, etc.). Project Grade: 90.
2008 – 2009 Tel Aviv University final project
Final project: ”Smart House”- home automation system.
 Distance control of home devices by cell phone using SMS message.
 Device included: cell modem (RS-232 communication), FPGA programmable device
FLEX70K/Altera, detectors (temperature, movement, light).
 RTL Design and Verification (Functional & GLS) by VHDL on ModelSim.
 Synthesis and P&R by QuartusII (Altera).
 Analog circuits: conversion TTL to RS-232 by ADM 202 convertor,.
EDUCATION
2010– 2012 MBA , Tel Aviv University. Current grade: 86.
Specialization: Financing, market research, investments on stock market.
2004 – 2009 B.Sc. in Electrical and Electronics Engineering, Tel Aviv University. Final grade: 82.
Specialization: VLSI, Digital and Analog Communication, Optoelectronics.
Relevant courses: VLSI Technologies (93).
MISCELLANEOUS
Languages  Hebrew English Russian
Army Service  Complete regular army service as a fighter and a commander in “Shaked - Givaty” ( 2001 –2003 )
Personal Skills  Organized and responsible
 Independent, innovative and fast learner
 Strong communications skills and team player
Languages and  Back End tools: Talus (Magma), Prime Time (Synopsys), Calibre
CAD Tools  Languages: VHDL, VerilogHDL (Design and Verification), C, Tcl.
 VLSI CAD tools: ModelSim (Mentor), QuartusII (Altera), Design Compiler (Synopsys)
 Mathematic tools: MATLAB.

2.  OS: Linux / Windows
 Test Equipment: Digital scope, Logic analyzer, Spectrum analyzer, Signal generator
Recommendations From Companies: Marvell, Chip Design College