This PrismTech Spectra software defined radio (SDR) webcast will discuss some of the challenges facing the migration or porting of an existing waveform to an Software Communications Architecture (SCA) radio system.
MADES Seminar @ Laboratory of Model-Driven Engineering Applied to Embedded Sy...Alessandra Bagnato
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Lieu: salle 1073 (Nano-innov – Bat. 862)
Date: 24 Septembre 2012
Heure: 14:00 – 15:00
Orateur: Alessandra Bagnato
Titre: UML, SysML and MARTE in Use, a High Level Methodology for Real-time and Embedded Systems
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Résumé/Abstract
Rapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new methodologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects.
The proposed seminar aims at presenting the development context and needs that have fostered the creation of a methodology and a set of UML, SysML and MARTE model-based diagrams within the research and development work carried out EU funded MADES project [http://www.mades-project.org/] which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries.
The seminar aims at highlighting the current practice and needs in real Avionics development case studies and in particular takes advantage of the vision of an avionics system integrator, highlighting the perspective of the different needs of its different customers within the Avionics industry that have been taken as a basis to build the methodology and the set of diagrams.
The MADES Project is expected to deliver important improvements in each phase of embedded systems development lifecycle by providing new tools and technologies that support design, validation, simulation, and code generation, while providing better support for component reuse.
MADES technologies are expected to reduce development costs of complex embedded systems for the Aerospace, Defence and other key European industries, while enabling a next generation of highly complex embedded systems to be developed that are more reliable, yet costing less to maintain and evolve as industry needs change and hardware capabilities increase.
Verteilte Synchronisierung von Modellen in automatisierten EntwicklungsprozessenIntland Software GmbH
ModelBus is a model-driven tool integration framework that allows for the seamless integration of development tools. It is based on service-oriented architecture principles and standards to enable the plugging in of commercial off-the-shelf tools to automate development processes. ModelBus provides services like transformation, simulation, and testing and supports capabilities like notification, access control, and synchronization across tools and repositories.
The document discusses architecture-centric software development processes. It describes traditional waterfall and iterative development models, and notes that iterative models allow for more flexibility to changing requirements. Agile development methods like eXtreme Programming (XP) are discussed, which emphasize iterative development, collaboration, and rapid delivery of working software. Key practices of XP are outlined, including user stories, testing, pair programming, refactoring, and continuous integration. The role of architecture in agile processes is also addressed.
A framework for distributed control and building performance simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
This document describes the career journey and experiences of Petros Maragkoudakis. It outlines his educational background in engineering and various roles he has held related to software engineering, testing, and project management. It provides details on the locations he has worked, technologies used, and certifications obtained throughout his career.
The document summarizes IBM's Rational Software Conference 2009. It discusses challenges in embedded software development like requirements shifts, low memory footprints, and debugging difficulties. It introduces IBM Rational Test RealTime as a solution that allows automated component testing at all levels from simple functions to distributed systems. It also enables runtime analysis through profiling, tracing, and linking of code, tests, and models. The tool aims to help developers test throughout development rather than just debugging later, to catch issues early and ensure quality and stability of embedded software projects.
Verifying Architectural Design Rules of a Flight Software Product LineDharmalingam Ganesan
This document discusses verifying architectural design rules of the Core Flight Software (CFS) product line. [1] It provides background on the CFS, which is a reusable flight software environment developed by NASA. [2] The analysis used tools to check that the CFS implementation follows documented rules regarding dependencies, decomposition, redundancy, and preprocessor usage. [3] It found some minor violations but concluded the CFS team performs rigorous design and code reviews.
This document provides an overview of computer aided manufacturing (CAM) systems and CNC machine tools. It discusses the history of CAM beginning in 1955 with the development of numerical control machines. Key developments include the APT programming language in 1959, direct numerical control in 1960, and the introduction of graphics-based CAM systems in the 1980s. The document also covers control systems, motion systems, machining centers, programming methods including APT and CAM, and the process of generating CNC toolpaths from CAD models.
MADES Seminar @ Laboratory of Model-Driven Engineering Applied to Embedded Sy...Alessandra Bagnato
-------
Lieu: salle 1073 (Nano-innov – Bat. 862)
Date: 24 Septembre 2012
Heure: 14:00 – 15:00
Orateur: Alessandra Bagnato
Titre: UML, SysML and MARTE in Use, a High Level Methodology for Real-time and Embedded Systems
-------
Résumé/Abstract
Rapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new methodologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects.
The proposed seminar aims at presenting the development context and needs that have fostered the creation of a methodology and a set of UML, SysML and MARTE model-based diagrams within the research and development work carried out EU funded MADES project [http://www.mades-project.org/] which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries.
The seminar aims at highlighting the current practice and needs in real Avionics development case studies and in particular takes advantage of the vision of an avionics system integrator, highlighting the perspective of the different needs of its different customers within the Avionics industry that have been taken as a basis to build the methodology and the set of diagrams.
The MADES Project is expected to deliver important improvements in each phase of embedded systems development lifecycle by providing new tools and technologies that support design, validation, simulation, and code generation, while providing better support for component reuse.
MADES technologies are expected to reduce development costs of complex embedded systems for the Aerospace, Defence and other key European industries, while enabling a next generation of highly complex embedded systems to be developed that are more reliable, yet costing less to maintain and evolve as industry needs change and hardware capabilities increase.
Verteilte Synchronisierung von Modellen in automatisierten EntwicklungsprozessenIntland Software GmbH
ModelBus is a model-driven tool integration framework that allows for the seamless integration of development tools. It is based on service-oriented architecture principles and standards to enable the plugging in of commercial off-the-shelf tools to automate development processes. ModelBus provides services like transformation, simulation, and testing and supports capabilities like notification, access control, and synchronization across tools and repositories.
The document discusses architecture-centric software development processes. It describes traditional waterfall and iterative development models, and notes that iterative models allow for more flexibility to changing requirements. Agile development methods like eXtreme Programming (XP) are discussed, which emphasize iterative development, collaboration, and rapid delivery of working software. Key practices of XP are outlined, including user stories, testing, pair programming, refactoring, and continuous integration. The role of architecture in agile processes is also addressed.
A framework for distributed control and building performance simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
This document describes the career journey and experiences of Petros Maragkoudakis. It outlines his educational background in engineering and various roles he has held related to software engineering, testing, and project management. It provides details on the locations he has worked, technologies used, and certifications obtained throughout his career.
The document summarizes IBM's Rational Software Conference 2009. It discusses challenges in embedded software development like requirements shifts, low memory footprints, and debugging difficulties. It introduces IBM Rational Test RealTime as a solution that allows automated component testing at all levels from simple functions to distributed systems. It also enables runtime analysis through profiling, tracing, and linking of code, tests, and models. The tool aims to help developers test throughout development rather than just debugging later, to catch issues early and ensure quality and stability of embedded software projects.
Verifying Architectural Design Rules of a Flight Software Product LineDharmalingam Ganesan
This document discusses verifying architectural design rules of the Core Flight Software (CFS) product line. [1] It provides background on the CFS, which is a reusable flight software environment developed by NASA. [2] The analysis used tools to check that the CFS implementation follows documented rules regarding dependencies, decomposition, redundancy, and preprocessor usage. [3] It found some minor violations but concluded the CFS team performs rigorous design and code reviews.
This document provides an overview of computer aided manufacturing (CAM) systems and CNC machine tools. It discusses the history of CAM beginning in 1955 with the development of numerical control machines. Key developments include the APT programming language in 1959, direct numerical control in 1960, and the introduction of graphics-based CAM systems in the 1980s. The document also covers control systems, motion systems, machining centers, programming methods including APT and CAM, and the process of generating CNC toolpaths from CAD models.
The document discusses how Soft Machines validated a VISCTM microprocessor design using Synopsys ZeBu emulation. It describes the emulation setup developed, including transactors to probe the design and a cosim framework to compare results with simulation. Various debug methodologies leveraging ZeBu's tools helped identify bugs early in emulation runs of tests, operating system boots, and benchmarks.
S-functions Presentation: The S-parameters for nonlinear components - Measure...NMDG NV
The document discusses S-functions, which are proposed as behavioral models for nonlinear components and applications, analogous to how S-parameters are used for linear components and applications. S-functions aim to simplify design and testing of nonlinear RF/microwave circuits by providing a uniform characterization approach, as S-parameters do for linear circuits. By extracting S-functions from a component, its nonlinear behavior can be modeled and its performance can be simulated, enabling more efficient system-level design and easier comparison to measurements during manufacturing testing. The document outlines benefits of the S-function approach and similarities to the established S-parameter methodology.
An ASAP Validation Implementation Approach by Qualit Consultingaesww
The document outlines key principles for good documentation practices in a regulated environment:
1. Documentation should be permanent, legible, accurate, prompt, clear, consistent, complete, direct, and truthful.
2. Key attributes of good documentation include that it cannot be changed, erased, or washed off; is easily readable; has correct calculations and carefully recorded information; has information recorded in a timely manner; has the same meaning for all readers; uses standardized formats to avoid confusion; includes all required information; records information directly rather than indirectly; and truthfully represents what occurred to the author's knowledge.
3. The document provides guidelines for documentation in compliance with Good Documentation Practices (GDP) regulations.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
The document discusses software architecture patterns and principles. It provides examples of how to apply Model-View-Controller (MVC), client-server, and other patterns to Android and web application development. Key strategies mentioned include refactoring existing code, separating concerns, and using patterns like observer and strategy to reduce coupling between architectural components.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
This document discusses improving security for tactical surveillance video while maintaining interoperability. It addresses challenges with upgrading thousands of existing receivers to support encrypted digital video, including logistics of replacement, comparable performance to analog, and secure key distribution. The document proposes that software defined radios can help by supporting multiple applications simultaneously during a transition period, implementing new waveforms that combine legacy and secure digital signals, and using software cryptography for on-the-fly key establishment similar to internet security. A commercial software defined radio example is presented that adds video devices and waveforms to an existing architecture.
This document provides information about the TACTICAL 2011 conference which will cover operational perspectives, waveform design, and upcoming tactical communications systems. The scope of the conference topics and expert international panel of speakers will make it an interesting and relevant event. Attendees can learn about major trends in future tactical networks and exchange information. The workshop on April 11th will focus on cognitive radio and its potential as the future of tactical communications, led by an expert from the University of York who has extensively researched this area.
This document discusses Roger Harris' work promoting rural information and communication technologies (ICTs) for poverty reduction in Asia since 1997. It provides an overview of Harris' projects in multiple Asian countries working with major aid agencies. The document then discusses key topics like poverty, the digital divide, examples of ICT implementations for development, issues around ICT strategies and sustainability, and Harris' approach to teaching and researching ICT4D.
This document provides an overview of Harris Corporation for investors attending the JPMorgan Basics and Industrials Conference on June 11, 2007. It outlines Harris' business segments and revenue mix, with government communications systems accounting for 45% of revenue. Projected revenue and earnings per share are provided for fiscal years 2007 and 2008, with growth expected in both. Engineering R&D investments are discussed, showing an increase from $111 million internally funded in FY04 to $188 million in FY06. Major new product introductions are highlighted.
Capnography measures ventilation by detecting exhaled carbon dioxide (CO2) and provides a graphical waveform that can be interpreted. Pulse oximetry measures oxygenation by detecting oxygen levels in the blood. Capnography is useful for confirming endotracheal tube placement, detecting tube displacement, assessing chest compressions during CPR, and detecting return of spontaneous circulation. It also helps evaluate and monitor respiratory conditions, hypoventilation states, and low perfusion states in intubated and non-intubated patients.
Automated planning, configuration, and monitoring
JENM: Network planning, configuration, and monitoring
JACS/ACES: Frequency management and spectrum planning
RBSAM: Radio battery and load planning
VMWare: Integrated virtual environment
Single User Interface: Common look and feel across tools
Mobile: Deployable on tactical laptops and servers
Scalable: Supports platoon to division level networks
Automated: Reduces manual processes and errors
Spread spectrum is a communication technique that spreads a narrowband communication signal over a wide range of frequencies for transmission then de-spreads it into the original data bandwidth at the receive.
The document discusses spread spectrum techniques used to prevent eavesdropping and jamming by adding redundancy. It describes two types of spread spectrum: Frequency Hopping Spread Spectrum (FHSS) which spreads signals across the frequency domain, and Direct Sequence Spread Spectrum (DSSS) which spreads signals across the time domain. The document then compares FHSS and DSSS in terms of performance, issues, acceptance and applications.
Frequency hopping spread spectrum (FH-SS) is a type of spread spectrum technique where the available channel bandwidth is divided into a large number of frequency slots arranged continuously. A transmitted signal occupies one or more of the available frequency slots, with the frequencies selected pseudo-randomly based on the output of a pseudo-noise generator. There are two types of FH-SS: slow FH-SS where one or more data bits are transmitted within one hop, and fast FH-SS where one data bit is divided over multiple hops. FH-SS provides advantages like improved interference rejection, code division multiplexing for CDMA, secure communication, and increased capacity and spectral efficiency. It is used in military communication systems, satellite communication,
Spread spectrum communication uses wideband noise-like signals that are hard to detect, intercept, or jam. It spreads data over multiple frequencies. There are two main techniques: direct sequence spread spectrum multiplies a data signal by a pseudorandom code, and frequency hopping spread spectrum modulates a narrowband carrier that hops between frequencies. Spread spectrum provides benefits like resistance to interference and jamming, better signal quality, and inherent security. It finds applications in wireless networks, Bluetooth, and CDMA cellular systems.
This presentation provides an overview of digital signal processing (DSP). It defines key terms like signal and signal processing and explains the basic principles and components of DSP systems. The presentation notes that DSP has advantages over analog processing like accuracy, flexibility, and ease of operation. It provides examples of DSP applications in areas like audio, communications, biomedicine, and more. In conclusion, the presentation emphasizes that DSP involves manipulating digital numbers using programmed instructions and is widely used in modern applications.
This document discusses digital signal processing (DSP). It begins by explaining that DSP involves converting an analog waveform into a series of discrete digital levels by measuring the amplitude of the waveform at regular intervals. It then provides examples of common DSP operations like convolution, correlation, filtering and modulation. The document notes key advantages of DSP like accuracy and reproducibility but also mentions disadvantages like cost and finite word length problems. It concludes by listing some common application areas for DSP like image processing, instrumentation/control, speech/audio processing, and telecommunications.
The document discusses cognitive radio and its benefits. It defines cognitive radio as a radio that is aware of its surroundings and adapts intelligently. Cognitive radio provides a framework for devices to dynamically create links by sensing the environment, evaluating options, and implementing the best waveform. This allows for improved spectrum utilization and quality of service. Some applications of cognitive radio include extending mobile networks, emergency radio systems, and multi-technology phones.
Yuan Yipeng has experience in GPU architecture, system algorithm implementation and optimization, embedded system design, automation testing, and digital logic design. He has worked at NVIDIA optimizing GPU performance modeling and verification, and at Huawei building an automation testing framework. He also has experience developing video acceleration and medical imaging projects while working at IBM.
The document discusses how Soft Machines validated a VISCTM microprocessor design using Synopsys ZeBu emulation. It describes the emulation setup developed, including transactors to probe the design and a cosim framework to compare results with simulation. Various debug methodologies leveraging ZeBu's tools helped identify bugs early in emulation runs of tests, operating system boots, and benchmarks.
S-functions Presentation: The S-parameters for nonlinear components - Measure...NMDG NV
The document discusses S-functions, which are proposed as behavioral models for nonlinear components and applications, analogous to how S-parameters are used for linear components and applications. S-functions aim to simplify design and testing of nonlinear RF/microwave circuits by providing a uniform characterization approach, as S-parameters do for linear circuits. By extracting S-functions from a component, its nonlinear behavior can be modeled and its performance can be simulated, enabling more efficient system-level design and easier comparison to measurements during manufacturing testing. The document outlines benefits of the S-function approach and similarities to the established S-parameter methodology.
An ASAP Validation Implementation Approach by Qualit Consultingaesww
The document outlines key principles for good documentation practices in a regulated environment:
1. Documentation should be permanent, legible, accurate, prompt, clear, consistent, complete, direct, and truthful.
2. Key attributes of good documentation include that it cannot be changed, erased, or washed off; is easily readable; has correct calculations and carefully recorded information; has information recorded in a timely manner; has the same meaning for all readers; uses standardized formats to avoid confusion; includes all required information; records information directly rather than indirectly; and truthfully represents what occurred to the author's knowledge.
3. The document provides guidelines for documentation in compliance with Good Documentation Practices (GDP) regulations.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
The document discusses software architecture patterns and principles. It provides examples of how to apply Model-View-Controller (MVC), client-server, and other patterns to Android and web application development. Key strategies mentioned include refactoring existing code, separating concerns, and using patterns like observer and strategy to reduce coupling between architectural components.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
This document discusses improving security for tactical surveillance video while maintaining interoperability. It addresses challenges with upgrading thousands of existing receivers to support encrypted digital video, including logistics of replacement, comparable performance to analog, and secure key distribution. The document proposes that software defined radios can help by supporting multiple applications simultaneously during a transition period, implementing new waveforms that combine legacy and secure digital signals, and using software cryptography for on-the-fly key establishment similar to internet security. A commercial software defined radio example is presented that adds video devices and waveforms to an existing architecture.
This document provides information about the TACTICAL 2011 conference which will cover operational perspectives, waveform design, and upcoming tactical communications systems. The scope of the conference topics and expert international panel of speakers will make it an interesting and relevant event. Attendees can learn about major trends in future tactical networks and exchange information. The workshop on April 11th will focus on cognitive radio and its potential as the future of tactical communications, led by an expert from the University of York who has extensively researched this area.
This document discusses Roger Harris' work promoting rural information and communication technologies (ICTs) for poverty reduction in Asia since 1997. It provides an overview of Harris' projects in multiple Asian countries working with major aid agencies. The document then discusses key topics like poverty, the digital divide, examples of ICT implementations for development, issues around ICT strategies and sustainability, and Harris' approach to teaching and researching ICT4D.
This document provides an overview of Harris Corporation for investors attending the JPMorgan Basics and Industrials Conference on June 11, 2007. It outlines Harris' business segments and revenue mix, with government communications systems accounting for 45% of revenue. Projected revenue and earnings per share are provided for fiscal years 2007 and 2008, with growth expected in both. Engineering R&D investments are discussed, showing an increase from $111 million internally funded in FY04 to $188 million in FY06. Major new product introductions are highlighted.
Capnography measures ventilation by detecting exhaled carbon dioxide (CO2) and provides a graphical waveform that can be interpreted. Pulse oximetry measures oxygenation by detecting oxygen levels in the blood. Capnography is useful for confirming endotracheal tube placement, detecting tube displacement, assessing chest compressions during CPR, and detecting return of spontaneous circulation. It also helps evaluate and monitor respiratory conditions, hypoventilation states, and low perfusion states in intubated and non-intubated patients.
Automated planning, configuration, and monitoring
JENM: Network planning, configuration, and monitoring
JACS/ACES: Frequency management and spectrum planning
RBSAM: Radio battery and load planning
VMWare: Integrated virtual environment
Single User Interface: Common look and feel across tools
Mobile: Deployable on tactical laptops and servers
Scalable: Supports platoon to division level networks
Automated: Reduces manual processes and errors
Spread spectrum is a communication technique that spreads a narrowband communication signal over a wide range of frequencies for transmission then de-spreads it into the original data bandwidth at the receive.
The document discusses spread spectrum techniques used to prevent eavesdropping and jamming by adding redundancy. It describes two types of spread spectrum: Frequency Hopping Spread Spectrum (FHSS) which spreads signals across the frequency domain, and Direct Sequence Spread Spectrum (DSSS) which spreads signals across the time domain. The document then compares FHSS and DSSS in terms of performance, issues, acceptance and applications.
Frequency hopping spread spectrum (FH-SS) is a type of spread spectrum technique where the available channel bandwidth is divided into a large number of frequency slots arranged continuously. A transmitted signal occupies one or more of the available frequency slots, with the frequencies selected pseudo-randomly based on the output of a pseudo-noise generator. There are two types of FH-SS: slow FH-SS where one or more data bits are transmitted within one hop, and fast FH-SS where one data bit is divided over multiple hops. FH-SS provides advantages like improved interference rejection, code division multiplexing for CDMA, secure communication, and increased capacity and spectral efficiency. It is used in military communication systems, satellite communication,
Spread spectrum communication uses wideband noise-like signals that are hard to detect, intercept, or jam. It spreads data over multiple frequencies. There are two main techniques: direct sequence spread spectrum multiplies a data signal by a pseudorandom code, and frequency hopping spread spectrum modulates a narrowband carrier that hops between frequencies. Spread spectrum provides benefits like resistance to interference and jamming, better signal quality, and inherent security. It finds applications in wireless networks, Bluetooth, and CDMA cellular systems.
This presentation provides an overview of digital signal processing (DSP). It defines key terms like signal and signal processing and explains the basic principles and components of DSP systems. The presentation notes that DSP has advantages over analog processing like accuracy, flexibility, and ease of operation. It provides examples of DSP applications in areas like audio, communications, biomedicine, and more. In conclusion, the presentation emphasizes that DSP involves manipulating digital numbers using programmed instructions and is widely used in modern applications.
This document discusses digital signal processing (DSP). It begins by explaining that DSP involves converting an analog waveform into a series of discrete digital levels by measuring the amplitude of the waveform at regular intervals. It then provides examples of common DSP operations like convolution, correlation, filtering and modulation. The document notes key advantages of DSP like accuracy and reproducibility but also mentions disadvantages like cost and finite word length problems. It concludes by listing some common application areas for DSP like image processing, instrumentation/control, speech/audio processing, and telecommunications.
The document discusses cognitive radio and its benefits. It defines cognitive radio as a radio that is aware of its surroundings and adapts intelligently. Cognitive radio provides a framework for devices to dynamically create links by sensing the environment, evaluating options, and implementing the best waveform. This allows for improved spectrum utilization and quality of service. Some applications of cognitive radio include extending mobile networks, emergency radio systems, and multi-technology phones.
Yuan Yipeng has experience in GPU architecture, system algorithm implementation and optimization, embedded system design, automation testing, and digital logic design. He has worked at NVIDIA optimizing GPU performance modeling and verification, and at Huawei building an automation testing framework. He also has experience developing video acceleration and medical imaging projects while working at IBM.
An Automatic Approach to Translate Use Cases to Sequence DiagramsMohammed Misbhauddin
An automatic approach is presented to translate use case descriptions to sequence diagrams. The approach uses a metamodel for use case specifications and sequence diagrams to guide the translation process. Key steps include parsing use case steps, identifying mapping rules between meta-models, and applying a translation process. An evaluation on sample student projects found the approach produced most sequence diagram constructs from use case sentences, addressing a gap between specification and design domains. Future work includes handling compound sentences and increasing classification rates using artificial intelligence.
HTAF 2.0 - A hybrid test automation framework.Mindtree Ltd.
HTAF is a test automation framework developed by Mindtree that bridges the gap between domain experts who lack automation expertise and automation experts who lack functional knowledge. It is a customizable framework built on HP QuickTest Professional that reduces the test automation lifecycle by accelerating script development, execution, and management through an intuitive interface and support for both data-driven and keyword-driven methodologies. Spreadsheet-driven tests can be created and executed by QA staff with minimal programming knowledge.
This document presents a model for evaluating the availability of automotive software architectures. The model is implemented as a reasoning framework in the ArchE architecture expert system. The model analyzes how effective watchdog mechanisms are in improving system availability when failures occur. A watchdog is a separate processor that monitors the main CPU and triggers a reset if the CPU fails. The model allows architects to quantitatively analyze how well their design meets availability requirements and identifies improvements to better handle failures.
The document discusses Model-driven Architecture building for constrained systems using the ARCADIA method. ARCADIA is a model-based architecture engineering approach that starts from standards like DoDAF and IEEE 1471, and integrates and enriches them with additional viewpoints and non-functional analysis capabilities. It allows collaborative validation of architectures through standards. The method involves formalizing and sharing operational and system needs models, and then developing logical and physical architecture models. These models can then be automatically analyzed using multiple viewpoints like safety, performance, and cost to validate and optimize the solution architecture.
A comprehensive formal verification solution for ARM based SOC design chiportal
This document discusses Jasper's formal verification solutions for ARM processor-based system-on-chip (SoC) designs. It describes how Jasper can be used at the IP level to verify ARM Cortex processors and at the system level to verify aspects of full SoCs such as protocol verification, deadlock detection, and connectivity verification. Customers mentioned include Ericsson, Apple, Sony, and AMCC.
Vayavya Labs is a company that develops system level design tools and provides embedded design services. It has created DDGEN, the world's first automated device driver generator, which can significantly reduce the cost and efforts required for device driver development. DDGEN takes hardware specification files as input and generates fully functional device drivers and test code. It supports a range of device complexities and operating systems. Pilot results found DDGEN provided close to 200-300% reductions in time and effort for driver development.
This document discusses the development cycle and tools used. It provides an overview of the software and hardware development tools, including editors, assemblers, compilers, linkers, simulators, emulators, debuggers, and more. The development cycle is explained as moving from market research and specification to development, testing, evaluation, and production. Testing is highlighted as taking a major portion of the development cycle. Development tools are also noted as being an important factor in shortening development time.
This document discusses model-based systems engineering (MBSE) and the use of system modeling languages. It motivates MBSE by describing how system models can integrate requirements, design, analysis and other engineering artifacts. It then provides an overview of the SysML modeling language and how it supports structural, behavioral, requirements and parametric modeling of systems. Finally, it describes how a system architecture model can act as an integrating framework to link various engineering analysis models across the lifecycle.
Component Based Distributed System DevelopmentEmmanuel Fuchs
The document discusses component-based development for large distributed systems. It describes using a component model with containers to define components and their interfaces. This allows components to be deployed across different platforms independently of their implementations. Visual design and deployment tools are proposed to manage components from design through integration and validation. The goal is to allow system development through assembly of pre-built components rather than custom engineering, reducing costs and skills requirements while improving quality.
R&M Technologies provides reliability, maintainability and logistics support analysis services. It developed RamLog software in 1992 to manage lifecycle logistics data. RamLog includes capabilities like FMECA, RCM analysis, maintenance task analysis, technical manual authoring, and a simulation edition to model system operations and support over the lifecycle. RamLog integrates with RAMLOG.NET for transactional database support.
A Graphical Language for Real-Time Critical Robot CommandsSerge Stinckwich
The document discusses a graphical language called GSRAPID for specifying complex robot commands. GSRAPID allows creating diagrams that define robot commands which are then compiled into Java code. It uses a model where robot commands are represented as nodes and connections in a graph. The language is implemented as an Eclipse plugin using the Graphical Modeling Framework. It allows parametrizing robot commands through a property editor and handles parameters that require method calls or variables through an interface called ISetter.
Calsoft Labs provides automotive product engineering services across various systems including telematics, infotainment, body electronics, and driver assistance systems. They have over 20 years of experience partnering with automotive OEMs and tier 1 suppliers. Calsoft Labs offers end-to-end product development capabilities from algorithm development to testing and validation on hardware-in-the-loop benches. They utilize flexible engagement models and a global delivery model to provide cost-effective solutions to customers.
1. The Java project developed a sales and distribution management system for an enterprise, migrating from a legacy Cobol/CORBA/DB2 system to a new Java/J2EE/Oracle architecture.
2. A quick ship shipment and tracking system for the shipping industry was developed using GWT, Spring, a custom ORM, Oracle RAC, and JBoss with integrated mapping, reporting and tracking features.
3. Both projects improved processes, centralized data access, and increased efficiency through redesigned architectures and user-friendly interfaces.
IRJET- A Review- FPGA based Architectures for Image Capturing Consequently Pr...IRJET Journal
This document presents a review of FPGA-based architectures for image capturing, processing, and display using a VGA monitor. It discusses using the Xilinx AccelDSP tool to develop the system on a Spartan 3E FPGA. The AccelDSP tool allows converting a MATLAB design into HDL for implementation on the FPGA. It summarizes the FPGA-based system architecture, which includes units for initialization, data transfer, image processing, and memory management. It then outlines the Xilinx AccelDSP design flow, which verifies the functionality at each stage of converting the floating-point MATLAB model to a fixed-point hardware implementation on the FPGA. The goal is to accelerate image processing applications using the parallel
NASA has increased its focus on standardized and disciplined engineering processes. SDA was developed to help NASA engineers easily follow rigorous processes with minimal overhead. It automates workflow and allows flexibility to handle exceptions. SDA supports modeling any software process, capturing best practices, and facilitating process execution and visibility for developers, teams, and managers. It has been used successfully at NASA to support processes, projects, and CMMI audits.
Relate: Architecture, Systems and Tools for Relative PositioningTill Riedel
The document discusses the RELATE software architecture which uses a modular design and blackboard for relative positioning measurements, the RELATE hardware architecture featuring a cube platform for integrating sensing modalities like ultrasound and magnetic, and a demo integrating ultrasound and magnetic sensing on the cube platform.
Varkon Semi provides design services and intellectual property for broadband physical layer implementations. Their services include system and architecture design, modeling, and full chip PHY design for technologies like WiFi, WiMAX, Bluetooth, and LTE. They have experience with projects involving ARM programming, DSP subsystems, analog and digital front ends, and host interfaces.
The document provides a summary of an experienced software engineer with over 10 years of experience in systems engineering, real-time software development, testing and project consulting. The engineer has expertise in model-based development, systems engineering, testing and collaboration tools from IBM Rational. Several projects are summarized involving development of combat management systems, model-based systems engineering, model-driven development, collaborative lifecycle management and static analysis.
The document summarizes a presentation given at a Business Analyst Conference on requirement traceability matrices. It defines what a traceability matrix is, describes the components of requirements that need to be traced, and provides an example matrix. It explains why traceability is important for requirements management, change impact analysis, and ensuring quality. While traceability was once seen as a paperwork exercise, it now enables better project control and process improvement when used with requirements management tools.
Similar to Migrating Legacy Waveforms to the Software Communications Architecture (SCA) (20)
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2. The Software Communications Architecture 2
The adoption of the SCA as a common
software infrastructure for software defined
radios continues to grow.
Porting an SCA waveform between two
platforms is not necessarily a
straightforward process.
Migrating legacy, non-SCA waveforms to
an SCA environment presents some
additional challenges in making the
existing waveform SCA compliant.
Copyright PrismTech 2011
3. SCA Waveform Portability 3
The Dream
Waveform implementations would be reusable across
multiple radio systems.
No modifications would be necessary to bring the
waveform up on another system.
The Reality
Initially, SCA waveform implementations were not
reusable.
Extensive modifications were required.
There seemed to be no correlation between use of
the SCA and portability of the waveform.
Copyright PrismTech 2011
4. The Problem… 4
The architecture and design of a Software
Defined Radio has multiple perspectives:
Processors
GPP, DSP, FPGA
Design Paradigms
Sequential Stack State Machine v. Parallel State
Machine
Implementation Languages
C/C++, HDL, SystemC
Systems Engineering
Hardware and software engineering architecture tasks
are performed semi-independently of each other.
Copyright PrismTech 2011
5. General Waveform and Radio Design Flow 5
analysis Wav eform Dev elopment
Waveform Radio
Modeling and simulation of Requirements specification
core waveform algorithms guide
and analysis. Initial hardware
in MATLAB, SIMULINK, «flow» architecture, processor types,
Mathematica, System Platform
Waveform «flow» identify performance and form
View, etc. «flow» Requirements
Requirements factor constraints
Functional Block
Grouping of algorithm Algorithm Achitecture
elements into logical Development Make / buy tradeoff
waveform components. analyses, preliminary
Use of UML component hardware prototype, basic
modeling techniques and electrical design, power
tools. Functional Block budget, etc.
Architecture Hardware
Selection
Non-real-time
implementation in C/C++ Functionally equivalent engineering
MATLAB, SIMULINK, Formal qualifications prototype (not to form factor), develop final
Prototype Bill of Materials (BOM). Base platform
Mathematica, testing, air interface
Waveform software implemented, e.g. device drivers,
SystemView, etc. testing by regulatory Engineering board support packages, SCA
body, e.g. Joint Prototype
Interoperability Test infrastructure software including SCA
Allocation of functional devices and services.
waveform components to a Deployment Command (JITC) for JTRS
processor type: GPP, Allocation radios.
DSP, FPGA, GPU, etc.
Integrated Air interface compliance, RF
System Testing Form Factor performance, error rates,
Target language selection, Code Design and Implementation
real-time prototyping, Development throughput, etc.
detailed design and
implementation.
Implement SCA waveform
component architecture.
system level verification,
test and integration.
Manufacturing
«process»
Copyright PrismTech 2011
6. Platform v. Waveform Development 6
analysis Wav eform Dev elopment
Waveform Radio
Modeling and simulation of Requirements specification
core waveform algorithms guide
and analysis. Initial hardware
in MATLAB, SIMULINK, «flow» architecture, processor types,
Mathematica, System Platform
Waveform «flow» identify performance and form
View, etc. «flow» Requirements
Requirements factor constraints
Functional Block
Grouping of algorithm Algorithm Achitecture
elements into logical Development Make / buy tradeoff
waveform components. analyses, preliminary
Use of UML component hardware prototype, basic
modeling techniques and electrical design, power
tools. Functional Block budget, etc.
Architecture Hardware
Selection
Non-real-time
implementation in C/C++ Functionally equivalent engineering
MATLAB, SIMULINK, Formal qualifications prototype (not to form factor), develop final
Prototype Bill of Materials (BOM). Base platform
Mathematica, testing, air interface
Waveform software implemented, e.g. device drivers,
SystemView, etc. testing by regulatory Engineering board support packages, SCA
body, e.g. Joint Prototype
Interoperability Test infrastructure software including SCA
Allocation of functional devices and services.
waveform components to a Deployment Command (JITC) for JTRS
processor type: GPP, Allocation radios.
DSP, FPGA, GPU, etc.
Integrated Air interface compliance, RF
System Testing Form Factor performance, error rates,
Target language selection, Code Design and Implementation
real-time prototyping, Development throughput, etc.
detailed design and
implementation.
Implement SCA waveform
component architecture.
system level verification,
test and integration.
Manufacturing
«process»
As a organization becomes proficient using the SCA, there is a
tendency to evolve towards an organizational model built around
a Platform (radio) team and a Waveform (application) team.
Copyright PrismTech 2011
7. SCA Influence on WF and Radio Design 7
analysis Wav eform Dev elopment
Waveform Radio
Modeling and simulation of Requirements specification
core waveform algorithms guide
and analysis. Initial hardware
in MATLAB, SIMULINK, «flow» architecture, processor types,
Mathematica, System Platform
Waveform «flow» identify performance and form
View, etc. «flow» Requirements
Requirements factor constraints
Functional Block
Grouping of algorithm Algorithm Achitecture
elements into logical Development Make / buy tradeoff
waveform components. analyses, preliminary
Use of UML component hardware prototype, basic
modeling techniques and electrical design, power
tools. Functional Block budget, etc.
Architecture Hardware
Selection
Non-real-time
implementation in C/C++ Functionally equivalent engineering
MATLAB, SIMULINK, Formal qualifications prototype (not to form factor), develop final
Prototype Bill of Materials (BOM). Base platform
Mathematica, testing, air interface
Waveform software implemented, e.g. device drivers,
SystemView, etc. testing by regulatory Engineering board support packages, SCA
body, e.g. Joint Prototype
Interoperability Test infrastructure software including SCA
Allocation of functional devices and services.
waveform components to a Deployment Command (JITC) for JTRS
processor type: GPP, Allocation radios.
DSP, FPGA, GPU, etc.
Integrated Air interface compliance, RF
System Testing Form Factor performance, error rates,
Target language selection, Code Design and Implementation
real-time prototyping, Development throughput, etc.
detailed design and
implementation.
Implement SCA waveform
component architecture.
system level verification,
test and integration.
Insertion points for SCA
implementation however….
Manufacturing
«process»
Copyright PrismTech 2011
8. SCA Influence on WF and Radio Design 8
… the SCA must be factored
analysis Wav eform Dev elopment
Waveform the radio and waveform
into Radio
Modeling and simulation of Requirements specification
core waveform algorithms
in MATLAB, SIMULINK,
process before
architecture«flow»
guide
and analysis. Initial hardware
architecture, processor types,
Mathematica, System the insertion points. Platform
«flow» Waveform
«flow» identify performance and form
View, etc. Requirements
Requirements factor constraints
Functional Block
Grouping of algorithm Algorithm Achitecture
elements into logical Development Make / buy tradeoff
waveform components. analyses, preliminary
Use of UML component hardware prototype, basic
modeling techniques and electrical design, power
tools. Functional Block budget, etc.
Architecture Hardware
Selection
Non-real-time
implementation in C/C++ Functionally equivalent engineering
MATLAB, SIMULINK, Formal qualifications prototype (not to form factor), develop final
Prototype Bill of Materials (BOM). Base platform
Mathematica, testing, air interface
Waveform software implemented, e.g. device drivers,
SystemView, etc. testing by regulatory Engineering board support packages, SCA
body, e.g. Joint Prototype
Interoperability Test infrastructure software including SCA
Allocation of functional devices and services.
waveform components to a Deployment Command (JITC) for JTRS
processor type: GPP, Allocation radios.
DSP, FPGA, GPU, etc.
Integrated Air interface compliance, RF
System Testing Form Factor performance, error rates,
Target language selection, Code Design and Implementation
real-time prototyping, Development throughput, etc.
detailed design and
implementation.
Implement SCA waveform
component architecture.
system level verification,
test and integration.
Insertion points for SCA
implementation however ….
Manufacturing
«process»
Copyright PrismTech 2011
9. What are the aspects of waveform porting? 9
Adherence to the SCA promotes portability
but does not guarantee it, i.e. it is
necessary but not sufficient.
Hardware abstraction is insufficient.
Migrating non-SCA legacy waveforms to
an SCA environment presents some
additional challenges.
Let’s start by looking at porting an SCA-
compliant waveform from one SCA radio to
another. Copyright PrismTech 2011
10. Source versus Target Radio Platforms 10
analysis Wav eform Dev elopment
analysis Wav eform Dev elopment
Waveform
Radio
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
Development Functional Block
Achitecture
Functional Block Waveform developed and
Architecture
then integrated with an Hardware
SCA compliant radio. Selection
Prototype
Waveform
Target radio may have a Engineering
Prototype
Deployment
Allocation
different implementation of
the SCA, hardware
Integrated
System Testing
architecture, memory, etc.
Code Design and Integrated
Development System Testing Form Factor
Implementation
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
11. Source versus Target Radios 11
analysis Wav eform Dev elopment
analy W
sis aveformDevelopment
Waveform
Radio
«flow» Waveform
Platorm
f
Requirements «flow»
Requirement
s
Algorithm
Development Functional Block
Achitecture
Functional Block
Architecture
Hardware
Selection
Prototype
Waveform
Engineering
Prototype
Deployment
Allocation
Integrated
Code Design and System Testing Integrated
Development Sys Tes
tem ting Form Factor
Implementation
Port
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
12. Source versus Target Radios 12
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design
Radio
and potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
Development Functional Block
Achitecture
Functional Block
Architecture
Hardware
Selection
Prototype
Waveform
Engineering
Prototype
Deployment
Allocation
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
13. Source versus Target Radios 13
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design
Radio
and potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
2) What are the physical transports?
Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
Hardware
Selection
Prototype
Waveform
Engineering
Prototype
Deployment
Allocation
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
14. Source versus Target Radios 14
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design
Radio
and potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
2) What are the physical transports?
Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture 3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
Prototype
configuration and control.
Waveform
Engineering
Prototype
Deployment
Allocation
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
15. Source versus Target Radios 15
analysis Wav eform Dev elopment
1) What are the processor differences?analysis Wav eform Dev elopment
Waveform Impacts development tools and design
Radio
and potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
2) What are the physical transports?
Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture 3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
Prototype
configuration and control.
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation refactoring control and I/O code out of functions
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Manufacturing
SCA waveform «process»
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
16. Source versus Target Radios 16
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
2) What are the physical transports?
Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture 3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
Prototype
configuration and control.
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation refactoring control and I/O code out of functions
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Differences in the radio hardware
Manufacturing
SCA waveform «process»
architecture (2) and degree detail in the Manufacturing
«process» SCA radio
SCA model of the hardware (3) can have
a significant impact on the time and cost
Copyright PrismTech 2011
required to port the waveform.
17. Source versus Target Radios 17
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform
Platform
Requirements «flow»
Requirements
Algorithm
2) What are the physical transports?
Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture 3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
Prototype
configuration and control.
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation refactoring control and I/O code out of functions
Integrated
Code Design and System Testing Integrated
Development System Testing Form Factor
Implementation
Port
Differences in the radio hardware
Manufacturing
SCA waveform «process»
architecture (2) and degree detail in the Manufacturing
«process» SCA radio
SCA model of the hardware (3) can have
a significant impact on the time and cost
Copyright PrismTech 2011
required to port the waveform.
18. Many of the concerns remain the same… 18
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform Platform
«flow»
Requirements Requirements
2) What are the physical transports?
Algorithm Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
configuration and control.
Prototype
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation
refactoring control and I/O code out of functions
Code Design and Integrated
System Testing Form Factor
Development Implementation
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
19. Many of the concerns remain the same… 19
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform Platform
«flow»
Requirements Requirements
2) What are the physical transports?
Algorithm Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
configuration and control.
Prototype
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation
refactoring control and I/O code out of functions
Code Design and Integrated
System Testing Form Factor
Development Implementation
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
20. Platform-specific elements in the waveform 20
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform Platform
«flow»
Requirements Requirements
2) What are the physical transports?
Algorithm Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
configuration and control.
Prototype
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation
refactoring control and I/O code out of functions
Code Design and
5) What is the existing logical protocol? Integrated
System Testing Form Factor
Development Effort required to move from a POSIX queue, as Implementation
an example, to CORBA.
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
21. Platform-specific elements in the waveform 21
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform Platform
«flow»
Requirements Requirements
2) What are the physical transports?
Algorithm Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
configuration and control.
Prototype
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation
refactoring control and I/O code out of functions
5) What is the existing logical protocol?
Integrated
Code Design and
Development
Effort required to move from a POSIX queue, as
System Testing Form Factor
Implementation
an example, to CORBA.
6) What is the implementation language(s)?
Impact if the waveform is in a different language than the
language used for the target radio, e.g. a mix of C/C++ may
require multiple ORB libraries, encapsulation strategies, etc.
Manufacturing
«process» SCA radio
Copyright PrismTech 2011
22. Platform-specific elements in the waveform 22
analysis Wav eform Dev elopment
1) What are the processor differences? Wav eform Dev elopment
analysis
Waveform Impacts development tools and design and
Radio
potentially deployment.
«flow» Waveform Platform
«flow»
Requirements Requirements
2) What are the physical transports?
Algorithm Functional Block
Development Impacts drivers and BSPs for Achitecture
middleware transports.
Functional Block
Architecture
3) What is the hardware abstraction level?
Hardware
Impacts waveform deployment model and Selection
configuration and control.
Prototype
Waveform
4) How modular is the waveform design?
Engineering
Impacts rebuilding for new processors and Prototype
Deployment
Allocation
refactoring control and I/O code out of functions
5) What is the existing logical protocol?
Integrated
Code Design and
Development
Effort required to move from a POSIX queue, as
System Testing Form Factor
Implementation
an example, to CORBA.
6) What is the implementation language(s)?
Impact if the waveform is in a different language than the
language used for the target radio, e.g. a mix of C/C++ may
require multiple ORB libraries, encapsulation strategies, etc.
Manufacturing
«process» SCA radio
7) What dependencies exist for OS and services?
Access to operating system calls in SCA is limited and services implemented
Copyright PrismTech 2011
on the source radio may not exist on the target radio.
23. Parameterizing Waveform Porting Effort 23
• Radio architecture differences impact waveform porting
effort in three areas*:
– Control – Change in control and synchronization of waveform components
– I/O – Change of data paths and transports Source $$$?? Target
– Processor – Change in algorithm
Modifying the I/O and
Control differences
between the source Processor
change
and target systems are
Control Architecture
($)
often the biggest cost DSP
FPGA
driver.
Model the waveform,
FPGA
the deployment, the DSP
I/O and Control
target radio hardware changes between
and asses the deltas. source and target
GPP GPP ($$$)
*The underlying assumption is that the
functional design of the waveform is not Processor Architecture
modified
Copyright PrismTech 2011
24. Reuse as a Cost Function 24
The cost of the reuse is driven by the differences
in the source and target platforms:
Processor – Algorithms, Waveform Design, Control
I/O – Physical bus, Data Marshalling, buffers
Control – Timing, Interrupts, Flow
Reuse does not imply zero cost.
If reuse of a waveform is viewed as a cost
function, can the advances in software cost
modeling over the past 25 years be applied.
Copyright PrismTech 2011
25. Reuse Cost Curve* 25
Relative Cost
1.0 Cost increases 1.0
Roughly 55% of the cost of
moderately up
development is attributable
about 75% of code
to reuse of approximately
change.
13% of the code!
0.75 0.70
0.55
0.5
There is roughly a 5%
The initial assumption was that
cost of reuse when no
there would be a (roughly) linear
changes are made!
relationship between the relative
cost and the percentage of code
modified.
0.25
*(Selby 85) analyzed the cost of reuse at NASA.
Approximately 3,000 software modules were
included in the analysis.
0.046
0.25 0.5 0.75 1.0
Percent Modified
Copyright PrismTech 2011
26. Waveform Network Layer Model 26
FM3TR Network Layers
Layer model provides
data_in data_out a view from the air
A/D boundary at the
data_in Nwk data_out PHY layer to the
Layer 3
Hci
nwk hci network layer.
in_from_dlc out_to_dlc
Much of the
in_from_nwk waveform processing
Layer 2
Dlc out_to_nwk
dlc hci can be performed in
rx_from_mac tx_to_mac high-level languages
on GPP or DSP
tx_from_dlc rx_to_dlc
Mac
mac hci
rx_from_phl
tc_to_phl
carrier_detect PHY layer typically
Layer 1
ends up on an FPGA
for more complex
tx rx
Phy waveforms, e.g.
phl hci carrier_detect
antenna Wideband Network
antenna
voice_in
Waveform (WNW)
voice_out
voice_in Copyright PrismTech 2011 voice_out
27. Waveform Component Model 27
External Layer FM3TR PHY Layer
interfaces define
primary boundary
«block»
between components «block» Phy::Cd
Phy::HCI
HCI input/output t_cd_on detect carrier detect
hci t_cd_on out to Mac
t_cd_off
tx_inc t_cd_off
config carrier
rx_inc
data_in data_out
data_in data_out
crc_inc
Layer 3
Nwk
Hci
nwk hci
in_from_dlc out_to_dlc
in_from_nwk
tx in from Mac
Layer 2
Dlc out_to_nwk
dlc hci
rx_from_mac tx_to_mac
tx_from_dlc
Mac rx_to_dlc
«block»
mac hci
Phy::Rx
rx_from_phl
tc_to_phl
«block»
carrier_detect
Layer 1
Phy::Tx rx_inc
rx
phl
tx
hci
Phy
carrier_detect in tx_inc crc_inc
antenna antenna
in
voice_in out
voice_out
out rx out to Mac
voice_in voice_out
«block»
Phy::Fsm
«block» config carrier
Phy::TransSec tx rx
trans_sec trans_sec voice_out
Internal layer analog
voice out «block»
interfaces may be API «block» Phy::Radio RF to/from
antenna
Phy::Ptt rf_freq rf_freq
calls or a message analog voice_in voice_out rf_out rf_out
antenna
voice_in rf_in
passing protocol voice in reset
rf_in
reset
Each layer has some
level of finite state
machine Copyright PrismTech 2011
implementation
28. Deployment Analysis 28
Once the waveform and the constituent
components have been logically modeled,
build a deployment model of the waveform
for the existing implementation.
The objective is to identify the deployment
dependencies related to processors,
physical transports and logical interfaces.
This provides a baseline for identifying
changes required to port to the new
platform.
Copyright PrismTech 2011
31. Processor Differences 31
Mapping the source deployment
components processors identifying any
existing dependencies on processor types,
operating systems and performance./
This provides the initial starting point for
identifying and assessing porting effort for
the functional components of the
waveform.
Copyright PrismTech 2011
33. Transport Protocols and Data Paths 33
Identifying the physical connections
between nodes, card assemblies and
processors delineates the physical
transports and transports.
This provides a baseline for comparison to
the target radio platform for identifying the
differences between the source and target
machines.
Copyright PrismTech 2011
35. Deployment Analysis 35
Specify current deployment information:
Processor type / model / memory / mips
Implementation language
Operating system (if applicable)
Identify other dependencies
Libraries and version
COTS packages (including IP cores on
FPGA)
Copyright PrismTech 2011
37. Logical Interfaces 37
Identify each pairwise set of interfaces
between waveform components
Describe interface:
Call direction (Uses / Provides port in SCA)
Synchronization (function return, delivery
only)
Content of call (parameters, description)
Build a map of dependencies (N2 chart,
sequence diagram)
Identify performance critical areas
Copyright PrismTech 2011
38. Summary 38
Porting a waveform is a superset of traditional,
i.e. GPP, software porting.
Lack of an industry standard for signal
processing hardware, e.g. standard protocols
and hardware abstractions, introduce
complexities requiring more detailed analysis.
Similar to traditional software cost estimation,
factors such as the level of experience the target
SDR radio and the existing waveform code
reduce porting effort and cost.
Although a complex problem, it is not intractable.
Copyright PrismTech 2011
39. SCA SDR Requires a Change in Mindset 39
Steve Jobs in Four Easy Steps
What the electronics industry can learn from his tenure at Apple
By G. Pascal Zachary / October 2011
“Jobs refused to accept that software and hardware were best designed
and engineered separately. For him, the venerable insight summarized by
Thomas Hughes, the grand historian of American technology, as `the system
must be first’ became a lodestar.”
The Inmates Are Running the Asylum: Why High-Tech
Products Drive Us Crazy and How to Restore the Sanity
Alan Cooper / 1999
Question: “What do you get when you cross a camera with a
computer?”
Answer: “A computer!”
“We don’t build radios anymore. We build computers that transmit.”
- Mark Turner, Harris
Copyright PrismTech 2011
40. What’s Next… 40
Following sessions will discuss
experience, approaches, techniques and
tools with respect to:
Modeling waveform software architecture
Potential for reverse engineering to assist in
the process
Deployment analysis to provide a “quick look”
assessment of complexity and potential effort.
Copyright PrismTech 2011
41. Further Information 41
For additional information on PrismTech’s
Spectra products and services:
E-mail:
info@prismtech.com
Website:
www.prismtech.com/spectra
Copyright PrismTech 2011