Jasmin Ibrahimovic is a senior design and verification consultant with over 20 years of experience in FPGA, SoC, and ASIC development. She specializes in hardware-assisted computing, interfaces, and microarchitectures. She has worked on mission-critical and carrier-class electronic products across various industries including computing, networking, wireless, and more. Her experience includes roles at Qualcomm, Chili.CHIPS, AMCC, Copper Mountain Networks, Nortel Networks, Gandalf Data, and Energoinvest/IRCA.

1. Senior Design & Verification Consultant: FPGA, SoC, ASIC, Embedded, High-Speed
Jasmin Ibrahimovic - jasmin@chili-chips.com - 7275 Calabria Court 65, San Diego, CA 92122, Phone 858 652 1699
20+ years in digital & embedded space, developing mission-critical & carrier-class electronic products
Specialized in FPGA, SoC, ASIC, hardware-assisted computing, interfaces and micro-architectures
High-energy, detail-savvy, pragmatic problem solver with passion for excellence, one who'll take the
challenge, embrace the change, keep the customer focus and roll-up the sleeves to make difference
Independent in execution, issue clearing, progress reporting, customer, vendor & team interactions
Front-end chip-level developer with solid system & application perspective
• ~ Feature, Feasibility, Performance, Trade-off Analysis
• ~ System Partitioning & Architecture
• ~ Interfaces & Handshakes
• ~ Putting the system together (IP, *RAM, MCU, Peripherals, High-Speed I/O, DDR1/2/3, PCIe, SerDes)
• ~ Modeling & Functional Simulation
• ~ Scripting
• ~ Constraints-driven Synthesis
• ~ Timing Analysis & Closure
• ~ Logic & Timing Design
• ~ RTL Coding
• ~ Bring-up. HW/SW integration & debug. Lab hands-on
• ~ Circuit & Schematic Design. Microcontrollers & Firmware. PCB-savvy
• ~ Chip lead and liaison to third parties
Senior Staff Design and Verification Engineer @ Qualcomm (formerly Rapid Bridge)
June 2010 – present, San Diego, California
+ Integration, verification, design of hard & soft IP subsystems & complete solutions: Mixed-signal, digital,
sea-of-gates using metal-programmable Gate Array kits (32nm and below)
+ Turn-key chip development, from concept to packaged silicon
+ Applications vary from computing, to networking, to wireless, to pre and post-sale customer support
Achievements: Key developer and customer-facing liaison for one-of-a-kind, solution for on-demand characterization
and adjustment of SoC power, performance, area, as well as fab yield. That product won the largest contract in the
Rapid Bridge history and ultimately led to successful acquisition by Qualcomm
> Completed refresher training in Synopsys Design Compiler and Prime Time SI
Senior Consultant @ Chili.CHIPS
March 2009 – June 2010, San Diego, California
+ FPGA design, verification, tool flow, implementation. Interface to sys, electrical, analog, PCB & FW teams
+ Xilinx Virtex6 (SX475T) with ISE12.2, Virtex5 (SX240T, LX220, SX50T, LX50) ISE11.4. Altera CPLDs with Quartus II 9.1
+ VHDL and SystemVerilog-2009 with OVM2.1 on Mentor ModelSim 6.5d and Cadence Incisive 8.2
+ Applications include SBC/COTS, industrial/military PC, image grabbing, PCIe, LPC/SERIRQ, DMA, SRIO, FMC
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2. Senior Design & Verification Consultant: FPGA, SoC, ASIC, Embedded, High-Speed
Achievements: Developed HDKs, integrated IP into and built custom apps on top of them. Processed data from 3GSPS
ADC, implemented DSP algorithms in FPGA and Rocket I/O HSSI. Created custom SuperIO controller for the 32nm Intel i7
Calpella mobile Xpress platform in a rugged VME/VPX form-factor with X/PMC sites. Interfaced to Xilinx PCIe and Aurora
macros on one side and driver firmware on the other
> Completed Intel MindShare training in PCI Express, including Gen2.0 additions
> Completed Altera training in Quartus II tool suite, C2H and PCIe on Arria2GX FPGAs
Principal Engineer @ AMCC
July 2006 – March 2009, San Diego, California
+ ASIC/SoC lead. RTL design and verification. Liaison to IP vendors, FW, PnR, analog & DSP/Sys teams
+ TSMC 65nm, 90nm, 130nm nodes in COT flow
+ Synopsys DC-Ultra. PrimeTime SI. Build scripts, constraints, timing closure. SDC, TCL, Perl, CSH
+ SystemVerilog-2005 with AVM on Mentor QuestaSim. Synopsys VCS for gate-level. Mentor Precision RTL
+ Applications include DDR2/3 SDRAM controller+PHY, 8051 with AMBA APB3, MoCA, 4x10GbE PHY, MDIO
Achievements: Architected standards-based, modular control plane for a 4-million gate ASIC. Devised transparent,
hardware-accelerated 8-to-16 bit bridging which boosted firmware throughput so that a low-end, 8-bit micro sufficed.
Automated CSR generation using Perl. Wrote APB transactors in SV and device drivers in Keil AX51 & C51.
Evaluated, procured and used IP for DDR2/3 SDRAM controller (soft) and PHY (hard). Worked with vendors and created
SOW + I/F spec. Wrote DC synthesis and PTSI sign-off scripts in TCL/SDC. Guided the P&R towards timing closure.
Worked with Product and Test Engineering to characterize the IP, which then integrated in the (AXI-based) SoC.
Led prototyping of a cable modem (MoCA) in a Virtex4 LX200 FPGA with discrete OFDM RF stage on a separate board.
Baseband processing included MAC with QAM2to256 data pump. Designed on-chip PowerPC 405 embedded subsystem
with DMA-enabled packet buffering. PPC ran the MAC layer (soft, in firmware) and DSP coefficient management.
> Received performance-based awards
Staff Engineer @ Copper Mountain Networks (now Motorola, Video Distribution Division)
October 2000 – June 2006, San Diego, California
+ FPGA/pSoC lead: Architecture, RTL design, verification. Methodology, scheduling/planning, mentoring
+ Xilinx Virtex2, Virtex2Pro, Spartan3, Virtex4 with 3.125GBaud SerDes and on-chip PowerPC405s
+ Verilog with OVA. ModelSim. Synplicity. EDK Platform Studio
+ Applications include dataplane fabric & post-processing for telco-grade IPTV delivery/access node platform
Achievements: Architected as a library of parameterized & reusable modules, the Fabric spanned some 20 distinct
FPGA designs distributed across a variety of SerDes-connected Switch, Processor and I/O cards. It contained complex
controllers and state machines, in select cases even employing multiple on-chip PowerPC 405 subsystems. It reconciled
the disparity of TCP/IP packets, ATM cells, TDM channels & MPEG transport streams. It glued, transformed, parsed
headers, disassembled/converged/reassembled traffic threads, classified, priority-routed, flow-controlled, de-jittered,
buffered in both on and off-chip RAM.
Interfaced to RF (QAM, AMVSB, QPSK), MTS, 6415 DSP (EMIF with DMA), xDSL, T1/E1, T3/E3, OC3/12/48, IMA,
10/100/1000 Ethernet, QDR SRAM, XAUI, SPI3, Intel IXP2800 CSIX, 1250 IXB/NP, APPI, SBI, POSPHY2, UTOPIA2.
Set-up functional simulation framework with clean, layered structure and comprehensive scope, which paid off in the
rapid board bring-up and bug-free final product.
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3. Senior Design & Verification Consultant: FPGA, SoC, ASIC, Embedded, High-Speed
As the lead of a team of 3, defined & instituted FPGA development process for design correctness, re-use, manageability
& portability. This resulted in significant time-to-market edge.
Through meticulous analysis of the functions to implement, achieved elegant simplicity and complexity without
complication… which opened the gates for doing more in less silicon & so helped the bottom line.
> Received formal training in System Verilog
> Received 'Leader of the Pack Award' for leading by example
> Received 'Certificate of Achievement' for succeeding to accommodate a major last-minute feature change
Senior Engineer @ Nortel Networks (Optical Networks Division)
July 1997 – Sept. 2000, Ottawa, Canada
+ ASIC/FPGA RTL design and verification. Liaison to FW, board and mixed-signal teams
+ 150nm (all-Cu) IBM ASIC flow with industry-first on-chip SerDes (also packaged as standalone hard IP macro)
+ Verilog and C. Actel
+ Applications include carrier-class SONET/SDH core-network node (OC192/768/1536, DWDM)
Achievements: Designed TSI, Framer block and clock control scheme (over 70 domains) with all timing handoffs for an 11-
million gate standard-cell ASIC. Served as liaison to 2.5Gbps SerDes macro design team, which then integrated.
Designed FPGA-assisted, software-laden numeric Stratum-3 PLL card. Used an array of Actel FPGAs and Motorola
PowerQUICC micro. Wrote all Verilog and some of the C device drivers.
> Received formal training in Verilog, Advanced Verilog, C, Perl, Synopsys VCS, DC, Prime Time, (formerly) Chrysalis
Equivalence Checker, Nortel COT flow, Nortel DFT, RF I, RF II, Assertiveness, Negotiations
Senior Engineer @ Gandalf Data Ltd. (now Mitel, Communications Infrastructure Division)
Sept. 1993 – June 1997, Ottawa, Canada
+ FPGA/PLD and circuit/schematics design. Direct interaction with FW, system, test and approvals’ teams
+ VHDL, AHDL, PALASM, Intel RISC. Lattice, Altera, Mentor, Viewlogic, OrCAD
+ Applications include edge network datacom/telecom (Terminal Server, Bridge, Router, ISDN PRI, POTS)
Achievements: Developed communications products based on Intel i960CF/HX RISC processor, Lattice (then Lucent)
ORCA2C FPGAs, Altera FLEX8K FPGAs, Intel Flash EPLDs and Altera MAX7K CPLD.
> Received formal training in VHDL, Exemplar synthesis, ViewLogic and Mentor Design Architect schematics
Design Engineer @ Energoinvest/IRCA
May 1989 – March 1993, Sarajevo, Bosnia-Herzegovina
+ Logic & circuit design in Able & OrCAD
+ Intel 80188. Programming in C, ASM86 and PL/M-86
+ Applications include ISDN BRI, Industrial Control, AX.25 and UHF/VHF TV transmission
BSEE, Control Theory & Electronics
Sept. 1984 - May 1989, University of Sarajevo, Bosnia-Herzegovina
+ Endorsed by US Department of Labor and University of Toronto, Canada. Graduated with Honors
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4. Senior Design & Verification Consultant: FPGA, SoC, ASIC, Embedded, High-Speed
Motorola/VideoDistributionDivision
Mitel/Communications Infrastructure Division
www.etf.unsa.ba
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