A seminar on VLSI design (VHDL) is organized to enhance the careers of engineering students by providing insights into modeling digital systems. The document outlines the distinctions between VHDL and other programming languages, emphasizing its ability to model complex systems and avoid design errors through various methodologies. It also covers aspects of synthesis, testing, and the advantages of VHDL in engineering applications.

1. A market leader in the field of technical training is glad to
organize a seminar on VLSI Design (VHDL) to shape the career
of bright students and to turn them into a great engineer. We
hope to have a good time with you..!!!
Your concern and co-operation is highly valuable to us.
___________
Team CETPA

3. *The above two are considered as a very difficult
tasks in the field of electronics engineering, where
in fact it’s a very simple technology.

4.  VHDL is for coding models of a digital system.
 Reasons for modeling:
◦ Requirements specification
◦ Documentation
◦ Testing using simulation
◦ Formal verification
◦ Synthesis
 Goal:
◦ Most ‘reliable’ design process, with minimum cost
and time
◦ Avoid design errors!

5.  VHDL is a programming language that allows one
to model and develop complex digital systems in a
dynamic environment.
 Object Oriented methodology for you C people can
be observed -- modules can be used and reused.
 Allows you to designate in/out ports (bits) and
specify behavior or response of the system.

6.  C is procedural language whereas VHDL is semi
concurrent & semi sequential language.
 C is Case Sensitive whereas VHDL is case
insensitive.
 There are some similarities, as with any
programming language, but syntax and logic are
quite different.

7. • Interfaces (PORTS)
• Behavior
• Structure
• Test Benches
• Simulation
• Synthesis

8. Dataflow
Behavioral
Structural
Kind of BORING sounding huh??
Well, it gets more exciting with the details !!
:)

9. Uses statements that defines the actual
flow of data.....
such as,
x <= y -- this is NOT less than equal to
-- told you its not C
this assigns the Boolean signal x to the value of
Boolean signal y... i.e. x = y
this will occur whenever y changes....

10. Entity declaration…
(Describes the input/output ports of a module)
entity name port names port mode (direction)
entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
punctuation
port type
reserved words

11.  Architecture body
 Describes an implementation of an entity
 May be several per entity
 Behavioral architecture
 Describes the algorithm performed by the
module
 Contains
Process statements, each containing
 Sequential statements, including
Signal assignment statements and
Wait statements

12.  Omit entity at end of entity declaration.
 Omit architecture at end of architecture body.
 Omit is in process statement header.
entity reg4 is architecture behav of reg4 is
port ( d0, d1, d2 : in bit begin
d3, en, clk : in bit; process (d0, ... )
q0, q1, q2, q3 : out bit ...
); begin
end reg4; ...
end process ;
end behav;

13.  Structural architecture
implements the module as a composition of
subsystems
contains
○ signal declarations, for internal interconnections
the entity ports are also treated as signals
○ component instances
instances of previously declared entity/architecture pairs
○ port maps in component instances
connect signals to component ports

14.  An architecture can contain both behavioral
and structural parts
Process statements and component instances
○ Collectively called concurrent statements
Processes can read and assign to signals
 Example: register-transfer-level (RTL) model
Data path described structurally
Control section described behaviorally

15. multiplier multiplicand
shift_reg
control_ shift_
section adder
reg
product

16. • Testing a design by simulation
• Use a test bench model
– A model that uses your model
– Apply test sequences to your inputs
– Monitors values on output signals
• Either using simulator.
• Or with a process that verifies correct operation
• Or logic analyzer.

17.  Discrete event simulation
Time advances in discrete steps.
When signal values change—events occur.
 A processes is sensitive to events on input
signals
Specified in wait statements.
Resumes and schedules new values on output
signals.
○ Schedules transactions.
○ Event on a signal if value changes.

18. Initial Design Entry VHDL, Schematic, State Diagram
Optimize Boolean Expression
into a standard form
Logic Optimization - To optimize area or speed
Minimized Blocks
Technology Mapping - To minimize area
Where the logic block is placed ?
Placement - With optimum routing wire
Connection between cells
Routing - To minimize area.
Used to configure the final
Programming Unit circuit

21. • Implement the VHDL portion of coding for synthesis.
• Identify the differences between behavioral and
structural coding styles.
• Distinguish coding for synthesis versus coding for
simulation.
• Use scalar and composite data types to represent
information.
• Use concurrent and sequential control structure to
regulate information flow.
• Implement common VHDL constructs (Finite State
Machines [FSMs], RAM/ROM data structures).

22. • Executable specification.
• Functionality separated from implementation.
• Simulate early and fast (Manage complexity)
• Explore design alternatives.
• Get feedback (Produce better designs)
• Automatic synthesis and test generation (ATPG for
ASICs)
• Increase productivity (Shorten time-to-market)
• Technology and tool independence.
• Portable design data (Protect investment)

23. • Digital Signal Processing.
• IC Testing & Analysis.
• FPGA Design Verification.
• FPGA Development.
• Hardware Design.
• IC designing.
• ASIC Development.

24. • THANK YOU
E-Mail
Gaurav_rai@live.com
•