The document is a seminar report on FPGA technology in outer space applications. It discusses the history and evolution of FPGA technology over time, including increasing gate densities and falling prices. It describes typical FPGA architecture which includes configurable logic blocks, interconnects, and I/O pads. Modern FPGAs integrate additional resources like memory blocks, DSP slices, and soft processor cores. The document highlights applications of FPGAs in aerospace, including COTS boards and development kits. It also outlines future potential for FPGAs in more complex roles in space systems.
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This is a presentation on FPGA from my 3rd year academics which was the field of my mini project/seminar in the same. Main emphasis is laid on the application of FPGA in DSP domain
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This is a presentation on FPGA from my 3rd year academics which was the field of my mini project/seminar in the same. Main emphasis is laid on the application of FPGA in DSP domain
"Field Programmable Gate Array (FPGA)" devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation.
This presentation contains the basics of FPGA design, what are HDL [hardware description languages], how VHDL design works on FPGA, what are the high tech applications, FPGA R & D opportunities, latest FPGA tools, resources and the National Activities on FPGA happened at Nepal.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
"Field Programmable Gate Array (FPGA)" devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation.
This presentation contains the basics of FPGA design, what are HDL [hardware description languages], how VHDL design works on FPGA, what are the high tech applications, FPGA R & D opportunities, latest FPGA tools, resources and the National Activities on FPGA happened at Nepal.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal1
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to
describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on
an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL
code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show
that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is
given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC.
The Field Programmable Gate Array (FPGA) industry is expanding both in market share and in innovation. The tailored FPGA features make them a better choice to include FPGA in an increasing number of applications in the upcoming years. A constant development of FPGA technology has led to minimize the gap of performance levels between FPGA and Application Specific Integrated Circuit (ASIC). Hence, in recent years, FPGA based platforms are proven more attractive than ASICs since their performance is high in addition to the low cost of the development process and short time to market. Therefore, nowadays, FPGA is highly attractive for a huge range of applications in communications, computing, avionics, security, automotive and consumer electronics. Field Programmable Gate Array industry has shown a steady growth with a market prediction value of USD 9 billion by 2023. Currently, the FPGA companies started growing in reserch areas such as Artifitial Intelligence (AI), Internet of Thing (IoT) and LIght Detection and Ranging (LIDAR). The aim of this paper is to review the developments in FPGA.
SMU DRIVE FALL 2017 MBA 205 – Operation research solved free assignment rahul kumar verma
SMU DRIVE FALL 2017 MBA 205 – Operation research solved free assignment
Define the Linear programming problem in operation Research. Also, explain various assumptions, advantages and limitations of linear programming problem.
A
Linear programming problem in operation Research
Assumptions of linear programming problem
Advantages of linear programming problem
Limitations of linear programming problem
2.5
2.5
2.5
2.5
10
2
a. Discuss the concept of Degeneracy in transportation problem
b. The ABC Tool Company has a sales force of 25 men who work out from Regional offices. The company produces four basic products lines of hand tools. Mr. Jain, the sales manager, feels that 6 salesmen are needed to distribute product line 1, 10 salesmen are needed to distribute product line 2, 4 salesmen to product line 3 and 5 salesmen to product line 4. The cost per day of assigning salesmen from each of the offices for selling each of the product lines are as follows
Regional office
Product Lines
푷ퟏ
푷ퟐ
푷ퟑ
푷ퟒ
푹ퟏ
20
21
16
18
푹ퟐ
17
28
14
16
푹ퟑ
29
23
19
20
Now, 10 salesmen are allowed to office 푹ퟏ , 9 salesmen to office 푹ퟐ, and 7 salesmen to office 푹ퟑ.
How many salesmen should be assigned from each office to selling each product line in order to minimize costs?
A
Degeneracy in transportation problem
Optimum allocation.
Optimum transportation cost
4
3
3
10
3
a. Elaborate the meaning of Simulation.
b. What are different Practical applications of simulation
A
Meaning of Simulation.
Practical applications of simulation
2
8
10
SET-II
1
a. Define the meaning of assignment problem in operation Research.
b. A Departmental head has four subordinates and four task to be performed. The subordinates differ in efficiency and the tasks differ in their intrinsic difficulty. His estimate of the times each man would take to perform each task is given in the following matrix-
Tasks
Subordinates
I
II
III
IV
A
8
26
17
11
B
13
28
4
26
C
38
19
18
15
D
19
26
24
10
How should the tasks be allocated to subordinates to minimize the total man-hours?
A
Description of assignment problem
Optimum allocation through Hungarian method
4
6
10
2
Define following criteria’s used for decision making under Uncertainty
a. Optimism (maximax or minimin) criterion
b. Pessimism (maximin or minimax) criterion
c. Equal probabilities (Laplace) criterion
d. Coefficient of optimism (Hurwicz) criterion
e. Regret (salvage) criterion
A
a. Optimism (maximax or minimin) criterion
b. Pessimism (maximin or minimax) criterion
c. Equal probabilities (Laplace) criterion
d. Coefficient of optimism (Hurwicz) criterion
2
2
2
2
10
SMU DRIVE FALL 2017 MBA 202 – financial management solved free assignmentrahul kumar verma
SMU DRIVE FALL 2017 MBA 202 – financial management solved free assignment
Financial planning means deciding in advance the financial activities to be carried on to achieve the basic objective of the firm. Explain the factors that affect financial planning.
Factors affecting Financial Plan
10
10
2.
“Book value is an accounting concept”. Explain the factors of this concept.
Calculate the worth of the value of one share from the below details of Company ABC :
Current dividend is Rs. 10.
It expects to have a supernormal growth period running to 6 years during which the growth rate would be 30%.
The company expects normal growth rate of 10% after the period of supernormal growth period. The investor’s required rate of return is 18%.
factors explaining the concept of book value
5
10
Solution to the problem
5
3.
Explain the Cash Flow Estimation Principles.
Cash Flow Estimation Principles.
10
10
Q. No
Assignment Set -2
Questions
Marks
Total Marks
1.
Explain EOQ and Re – order point.
A manufacturing company has an expected usage of 1,00,000 units of a certain product during the next year. The cost of processing an order is Rs 200 and the carrying cost per unit per annum is Rs 2. Lead-time for an order is five days and the company will keep a reserve of two days usage.
Calculate EOQ and Re – order point. Assume 250 days in a year.
Explanation of EOQ and Re – order point
5
10
Calculation of EOQ and Re – order point
5
2.
Explain the capital Budgeting process and its appraisals
Solve the below given problem:
Given below are the details on the cash flows of two projects A and B. Compute pay-back period for A and B.
Cash flows of A and B
Year
Project A cash flows (Rs.)
Project B cash flows (Rs.)
0
(4,50,000)
(5,50,000)
1
3,00,000
2,00,000
2
1,50,000
2,50,000
3
50,000
3,00,000
4
2,00,000
3,50,000
5
1,00,000
2,00,000
Explanation of capital budgeting process and its appraisals.
6
10
Solution for the problem
4
3.
From the below details, show the effect of the dividend policy on the market price of company XYZ Ltd. shares using the Walter’s Model.
Equity capitalisation rate Ke is 10%
Earnings per share is given as Rs. 10
ROI (r) may be assumed as follows: 10% and 15%
Show the effect of the dividend policies on the share value of the firm for three different levels of r, taking the DP ratios as 20%, 40%, 60%, 80% and 100%.
Explanation of concepts of working capital
10
10
SMU DRIVE FALL 2017 MBA 204 – management information systems solved free assi...rahul kumar verma
SMU DRIVE FALL 2017 MBA 204 – management information systems solved free assignment
What are the different challenges a manager face in managing Information systems?
Challenges faced by the manager in Managing Information systems
10
10
2
Explain the concepts of
a) Transaction Processing System
b) Management Information System
a) Transaction Processing System
5
10
b) Management Information system
5
3
How Information system can be used to support Competitive strategy? Substantiate with suitable examples.
Information system to support competitive strategy
6
10
Examples
4
SET - II
Q. No
Assignment Set – 2 Questions
Marks
Total Marks
1 Explain the following concepts
a) Electronic Data Interchange (EDI)
b) Online Payment Technology
c) Mobile Commerce
a) Electronic Data Interchange (EDI)
3
b) Online Payment Technology
4
c) Mobile Commerce
3
10
2
What is DSS? How it is different from MIS? How DSS helps in Decision making?
Decision Support System
2.5
10
Differences between MIS and DSS
2.5
DSS in Decision making
5
3
Explain why privacy is important for individuals in the organizations?
How workplace electronic monitoring is done in the organizations?
Explaining the reasons why privacy is important in the organizations
6
10
Explaining the ways in which electronic monitoring is done in the organizations
4
SMU DRIVE SPRING 2017 MBA 103- Statistics for Management solved free assignmentrahul kumar verma
ASSIGNMENT
DRIVE
SPRING 2017
PROGRAM
MBA
SEMESTER
I
SUBJECT CODE & NAME
MBA 103- Statistics for Management
BK ID
B1731
CREDIT & MARKS
4 CREDITS, 30 MARKS EACH
Note –The Assignment is divided into 2 sets. You have to answer all questions in both sets and submit as one document. Average of both assignments marks scored by you will be considered as your IA marks. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Set –I
Q.No
Criteria
Marks
Total Marks
1
Give the meaning of the word Statistics. Mention the characteristics of Statistics.
A
Meaning of Statistics
Characteristics of Statistics
4
6
10
2
a. What do you mean by Probability?
b. A bag contains 5 white, 6 red, 2 green and 2 black balls. Two balls are selected at random from the bag. Find the probability that the selected balls are-
i. White
ii. Red
A
a. What do you mean by Probability?
b. A bag contains 5 white, 6 red, 2 green and 2 black balls. Two balls are selected at random from the bag. Find the probability that the selected balls are-
i. White
ii. Red
4
3
3
10
3
What Do you mean by Sampling? Describe various Probability and Non- Probability Sampling Methods
A
Meaning of Sampling
Probability Sampling Methods
Non-Probability Sampling Methods
2
4
4
10
SET-II
1
Write short notes on
A
a. Type I and Type II error
b. Level of Significance
c. Null Hypothesis
d. Two–tailed Tests and One–tailed Tests
e. Test Statistics
a. Type I and Type II error
b. Level of Significance
c. Null Hypothesis
d. Two–tailed Tests and One–tailed Tests
e. Test Statistics
2
2
2
2
2
10
2
a. Explain The concept of One Way ANOVA.
b. Table given below depicts the data on production rate by five workmen on four machines. Test whether the rate is significantly different due to workers and machines.
Machines
Workmen
I
II
III
IV
V
1
46
48
36
35
40
2
40
42
38
40
44
3
49
54
46
48
51
4
38
45
34
35
41
A
Explanation of ANOVA
Numerical Solution
2
8
10
3
a. Explain the meaning of Weighted Index Numbers.
b. Information of sales price per unit of different commodities for two different years is given in following table-
Commodities
2010
2016
Price
Quantity
Price
Quantity
A
20
5
25
3
B
30
8
45
5
C
10
12
20
8
D
15
10
16
10
E
45
5
50
6
F
90
10
110
8
Construct the Price Index taking 2010 as the base year and 2016 as the current year by following methods.
i. Laspeyre’s Price Index
ii. Paasche’s Method
iii. Dorbish and Bowley’s method
iv. Fisher’s Ideal Index Method
A
a. Meaning of Weighted Index Numbers
b. Construction of the Price Index
i. Laspeyre’s Price Index
ii. Paasche’s Method
iii. Dorbish and Bowley’s method
iv. Fisher’s Ideal Index Method
2
2
2
2
2
10
*A-Answer
***********
SMU DRIVE SPRING 2017 MBA101– Management Process and Organizational Behavio...rahul kumar verma
ASSIGNMENT
Drive
SPRING 2017
Program
MBA
Semester
1
Subject code & name
MBA101– Management Process and Organizational Behaviour
Book ID
B1621
NUMBER OF ASSIGNMENTS, CREDITS & MARKS
2, 4 Credits, 30 marks each
Note –The Assignment is divided into 2 sets. You have to answer all questions in both sets and submit as one document. Average of both assignments marks scored by you will be considered as your IA marks. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Q. No
Assignment Set I
Questions
Marks
Total Marks
1
Explain the Definition and Importance of ‘management’.
Definition of Management
3
10
Importance of Management
7
2
Explain the steps involved in Planning process.
Discuss any 5 importance of Organizing.
The steps involved in Planning process
5
10
Importance of Organizing
5
3
Explain the following:
a) Definition pf Leading.
b) Importance of Leading.
Definition of Leading
3
10
Explanation of the importance of Leading
7
Q. No
Assignment Set II
Questions
Marks
Total Marks
1
Define the term Controlling? What are the prerequisites of effective control?
Definition of controlling
2
10
Pre-requisites of effective control
8
2
Explain the components and functions of attitude.
Explanation of the components of attitude
5
10
Explanation of the functions of attitude
5
3
Define leadership. Write a brief note on ‘Contingency Theories of Leadership’.
Definition of leadership
3
10
Contingency Theories of Leadership
7
ASSIGNMENT
DRIVE
SPRING 2017
PROGRAM
Master of Business Administration- MBA
SEMESTER
Semester 1
SUBJECT CODE & NAME
MBA105 - MANAGERIAL ECONOMICS
BK ID
B1625
CREDIT & MARKS
4 Credits, 30 marks
Note –The Assignment is divided into 2 sets. You have to answer all questions in both sets and submit as one document. Average of both assignments marks scored by you will be considered as your IA marks. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Assignment Set -1
Questions
Q.No
Questions
Marks
Total Marks
1
Explain the meaning and Features of demand forecasting?
Meaning Of demand Forecasting
3
Features of demand forecasting
7
10
2
Explain the cost output relationship and nature and behavior of cost curve in the short run with hypothetical cost schedule?
The cost output relationship and nature and behavior of cost curve in the short run with hypothetical cost schedule
10
10
3
Write short notes on:
a) Consumption Function
b) Investment Function
Define Consumption Function
5
Define Investment Function
5
10
Note – Answer all questions. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Note – Answer all questions. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Q.No
Assignment Set -2
Questions
Total Marks
1
What are the various role of fiscal policy in economic development?
10
Role of fiscal policy
10
2
Explain the law of variable proportions in detail with diagrammatic representation.
10
Law of variable proportions in detail with diagrammatic representation.
10
3
What are the various factors which bring changes in supply?
10
various factors which bring changes in supply
10
ASSIGNMENT
DRIVE
SPRING 2017
PROGRAM
Master of Business Administration- MBA
SEMESTER
I
SUBJECT CODE & NAME
MBA106 –Human Resource Management
BK ID
B1626
CREDITS & MARKS
4 Credits, 30 marks Each
Note –The Assignment is divided into 2 sets. You have to answer all questions in both sets and submit as one document. Average of both assignments marks scored by you will be considered as your IA marks. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.
Q.No
Assignment I
Questions
Marks
Total Marks
1
What is human resources management? Discuss the scope & functions of HRM.
1. Meaning of HRM
2. Scope of HRM
3. Functions of HRM
2
4
4
10
2
Describe the process of HR Planning. Explain HR Forecasting Techniques.
1. Process of HR Planning
2. HR Forecasting Techniques
4
6
10
3
What is succession planning? What are the benefits of having a formal Succession Planning System in an organization?
1. Meaning of Succession Planning
2. Benefits
4
6
10
Q. No
Assignment II
Questions
Marks
Total Marks
1
Discuss the basic guidelines of a Disciplinary policy
Explain the basic guidelines of a Disciplinary policy
10
10
2
Suppose you have joined as an HR and you have been assigned a task to carry out the grievance handling procedure in your organization. What according to you are the causes of Grievance? Describe in detail the Grievance handling procedure
Causes of Grievance
Explain the Grievance handling procedure
4
6
10
3
Write short notes on the following :
a)Job Enlargement
b)Job Enrichment
Concept of Job Enlargement
Concept of Job Enrichment
5
5
10
SMU DRIVE SPRING 2017 MBA102 - Business Communication free solved assignment rahul kumar verma
SMU MBA102 - Business Communication solved assignment
Define communication. What are the characteristics of communication?
Definition
Characteristics of communication
2
8
10
2
What are the five types of reading?
Five types of reading
2 * 5
10
3
Mention the advantages and disadvantages of intranet.
Advantages
Disadvantages
5
5
10
Q. No
Assignment Set -II
Questions
Marks
Total Marks
1
Explain the wheel of communication. Who are the internal stake holders in an organization?
Wheel of communication
Internal Stake Holders
2
8
10
2
Define meeting. Explain types of meetings.
Meeting
Types of meeting
2
8
10
3
Explain the barriers to listening.
Barriers to listening
10
10
Memory map selection of real time sdram controller using verilog full project...rahul kumar verma
full report on Memory map selection of real time SDRAM controller using verilog which was my project.If you want any help email me @ rahulverma2512@gmail.com
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
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Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
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Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
1. Page 1
JSS ACADEMY OF TECHNICAL EDUCATION
AND MANAGEMENT
NOIDA
Seminar Report
On
FPGA IN OUTER SPACE
Submitted by
RAHUL KUMAR VERMA
1009131069
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
2012-2013
2. Page 2
ABSTRACT
A quiet revolution is taking place. Over the past few years, the density of the
average programmable logic device has begun to skyrocket. The maximum number
of gates in an FPGA is currently around 500,000 and doubling every 18 months.
Meanwhile, the price of these chips is dropping. What all of this means is that the
price of an individual NAND or NOR is rapidly approaching zero! And the
designers of embedded systems are taking note.
The line between hardware and software has blurred. Hardware engineers create
the bulk of their new digital circuitry in programming languages such as VHDL
and Verilog and often target it to CPLDs and FPGAs.
As this trend continues, it becomes more difficult to separate hardware from
software. After all, both hardware and software designers are now describing logic
in high-level terms, albeit in different languages, and downloading the compiled
result to a piece of silicon. Surely no one would claim that language choice alone
marks a real distinction between the two fields.
3. Page 3
ACKNOWLEDGEMENT
I owe my sincere gratitude to my supervisor, Mrs. Suvarna N.A. (Assistant
professor, < Department of ELECTRONICS AND COMMUNICATION>,
JSSATE-NOIDA) who has constantly given me the encouragement, technical
guidance and moral support throughout my thesis work.
I would like to extend my heartfelt thanks and lifelong indebtedness to
Prof.Dinesh Chandra (HOD, Department of EC, JSSATE-NOIDA) for his
technical and moral support.
RAHULKUMARVERMA
1009131069
5. Page 5
4.2. High level language………………………………………..17
5.Modern Development Of FPGA…………………………...…17
5.1.The Xilinx Virtex-6 FPGA family……………………...……18
6.FPGA in Comparison To Other logic Devices…………….....19
7.Applications……………………………………….…………....20
7.1.Outer Space Application……………………………..20-21
7.2.FGPA-Based Development ……………………………...22
for Defenseand AerospaceApplications
7.2.1FPGA-Based COTS Boards……………...………………22
7.2.2 The FPGA Developers Kit………………...……………...23
8.Future Scope Of FPGA Technology……………………….…24
9.Major manufacturers………………………………..…..…...25
6. Page 6
10. CONCLUSION……..………………………………………………….26
11. REFERENCES………………………………………………………...27
1. INTRODUCTION TO FPGA
FPGA stands for Field Programmable Gate Array. An FPGA is an integrated
circuit (IC) that can be programmed and configured by the embedded system
developer in the field after it has been manufactured. FPGA is a semi-conductor
device which is not limited to any pre-defined hardware function; it is rather highly
flexible in its functionality and may be configured by the embedded system
developer according to his design requirements.
FPGAs use pre-built logic blocks and programmable routing channels for
implementing custom hardware functionality depending upon how embedded
system developer configure these devices. The FPGAs are programmed and
configured using hardware description languages (HDL) like Verilog and VHDL,
similar to that used for an application-specific integrated circuit (ASIC).
FPGAs give a lot of flexibility to the embedded systems developer to program
features and functions of their FPGA based product even after the FPGA based
product has been installed in the field. This is the reason why FPGA is termed field
programmable, as FPGA may easily be reconfigured and reprogrammed in the
7. Page 7
field according to new features and end-user’s requirements. FPGAs are being
widely used in digital electronic circuits and embedded systems design and FPGAs
have a well-defined place in every embedded system developer’s toolbox.
FPGAs may be used to implement any logical functions and features that an
Application-Specific Integrated Circuit (ASIC) could possibly be utilized to
implement. But in terms of flexibility of upgrading and modifying the functionality
and features of FPGAs, even after the FPGA based product has been shipped to the
end-user, FPGAs really have an edge over ASIC.
.
1.1. Field Programmable Gate Array
Field Programmable Gate Array
Field : ―in the field‖
Programmable : ―Re-Configurable‖ Change Logic Functions
Gate Array : reference to ASIC internal architecture
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing—hence "field-
programmable".
The FPGA configuration is generally specified using a hardware description
language (HDL), similar to that used for an application-specific integrated circuit
(ASIC). Contemporary FPGAs have large resources of logic gates and RAM
blocks to implement complex digital computations.
As FPGA designs employ very fast IOs and bidirectional data buses it becomes a
challenge to verify correct timing of valid data within setup time and hold time.
8. Page 8
Floor planning enables resources allocation within FPGA to meet these time
constraints.
FPGAs can be used to implement any logical function that an ASIC could perform.
The ability to update the functionality after shipping, partial re-configuration of a
portion of the design and the low non-recurring engineering costs relative to an
ASIC, offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"—somewhat like many (changeable) logic gates that can be inter-wired in
(many) different configurations. Logic blocks can be configured to perform
complex combinational functions, or merely simple logic gates like AND and
XOR. In most FPGAs, the logic blocks also include memory elements, which may
be simple flip-flops or more complete blocks of memory.
1.2. History OfFPGA
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of
being programmed in batches in a factory or in the field (field programmable),
however programmable logic was hard-wired between logic gates.
In the late 1980s the Naval Surface Warfare Department funded an experiment
proposed by Steve Casselmanto develop a computer that would implement 600,000
reprogrammable gates. Casselman was successful and a
patent related to the system was issued in 1992.
Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first
commercially viable fielprogrammable gate array in 1985 – the XC2064.[10] The
XC2064 had programmable gates and programmable interconnects between gates,
the beginnings of a new technology and market.
The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-
input lookup tables (LUTs).
9. Page 9
More than 20 years later, Freeman was entered into the National Inventors Hall of
Fame for his invention Xilinx continued unchallenged and quickly growing from
1985 to the mid-1990s.
The 1990s were an explosive period of time for FPGAs, both in sophistication and
the volume of production. In the early 1990s, FPGAs were primarily used in
telecommunications and networking.
1.3. Inventors
10. Page 10
Ross Freeman and Bernard Vonderschmitt
They invented the first commercially viable field programmable gate
array in 1985
2. Architecture and working
The most common FPGA architecture consists of an array of logic blocks (called
Configurable Logic Block) CLB, or Logic Array Block, LAB, depending on
vendor), I/O pads, and routing channels.
Generally, all therouting channels have the same width (number of wires). Multiple
I/O pads may fit into the height of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs/LABs and I/Os required is easily determined from the
design, the number of routing tracks needed may vary considerably even among
designs with the same amount of logic.
For example, a crossbar switch requires much more routing than a systolic array
with the same gate count. Since unused routing tracks increase the costof the part
without providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs
11. Page 11
can be routed.This is determined by estimates such as those derived from Rent's
rule or by experiments with existing designs.
2.1 Architecture
CLB: The Configurable logic blocks are were the user specific functions are
calculated.
IOB: The Input/Output block make it possible to connect the FPGA to the other
elements of the
application
Interconnect: Interconnect is essential for writing between CLB and from IOBs
to CLBs.
It is composed of a lookup table (LUT) controlled by 4 inputs to implement
combinational logic and a D-Flip-Flop for sequential logic.
A MUX is used to select between using the output of the combinational logic
directly and using the output of the Flip-Flop.
One CLB is programmed by downloading the truth table of the logical function to
the LUT (16bit) and the control bit of the MUX (1 bit). By using multiple copies of
the this structure any combinational and sequential logic circuit can be
implemented.
Additionally the LUT can also be used as memory.Once the CLB slices have been
configured to implement logical functions they have to be connected
to implement bigger logical function.
12. Page 12
In general, a logic block (CLB or LAB) consists of a few logical cells (called
ALM, LE, Slice etc.). A typical cell consists of a 4-input LUT, a Full adder (FA)
and a D-type flip-flop, as shown below.
The LUTs are in this figure split into two 3-input LUTs. In normal modethose are
combined into a 4-input LUT through the lefmux. In arithmeticmode, their outputs
are fed to the FA. The selection of mode is programmed into the middle
multiplexer.
The output can be either synchronous or asynchronous, depending on the
programming of the muxto the right, in the figure example. In practice, entire or
parts of the FA are put as functions into the LUTs In order to save space.
13. Page 13
ALMs and Slices usually contains 2 or 4 structures similar to the example figure,
with some shared signals. CLBs/LABs typically contains a few ALMs/LEs/Slices.
In recent years, manufacturers have started moving to 6-input LUTs in their high
performance parts, claiming increased performance.
Since clock signals (and often other high-fan-out signals) are normally routed via
special-purpose dedicate routing networks in commercial FPGAs, they and other
signals are separately managed.
For this example architecture, the locations of the FPGA logic block pins are
shown below. Logic Block
2.2Previous generation logic device
Simple Logic (used to ―glue‖ other ICs together)
Reprogrammable (UV light, electrically eraseable)
Cheap
14. Page 14
Easy to Program
Many different variations
Eg. Implement Logic as ‘Sum of Products’ Terms
2.2.1ASIC’s
Large Complex Functions
Customised for Extremes of Speed, Low Power
Very Expensive
PLDs
SPLDs CPLDs
PLAsPROMs PALs GALs etc.
a b c
&
&
&
a !a b !b c !c
a cb& &
a c&
!b !c&
Predefined AND array
Programmable
ORarray
Predefined link
Programmable link
l
l
l
w x y
w = (a & c) | (!b & !c)
x = (a & b & c) | (!b & !c)
y = (a & b & c)
15. Page 15
Very Hard to Design.
Long Design cycles.
Not Reprogrammable. High Risk
Fig. Block Diagram Of ASIC’S
3. Feature And Characterstics
1.Logic Elements
ASICs
Structured
ASICs
Gate
Arrays
Standard
Cell
Full
Custom
Increasing complexity
(a) Single-column arrays (b) Dual-column arrays
I/O cells/pads
Channels
Basic cells
Programmable
interconnect
Programmable
16. Page 16
Lookup Table
Flip Flops
Multiplexers
2.Memory Resources
SRAM blocks
3.Routing Resources
Hierarchy Programmable Channels between Logic Elements
Configurable I/O
Interfaces to the real world. Logic Levels. Fast Serial I/O
4.Massively Parallel Architecture (HEP)
5.Clocked Logic Design
6.CMOS based using SRAM cells for configuration
7.Fast Turnaround Designs
8.Mass produced.
9. Cheap
4. FPGA design and programming
FPGAs are not programmed directly. Synthesis tools translate the code into bit
stream, which is downloaded to the configuration memory of the FPGA.
Commonly, hardware description languages (HDL) are use to configure the device.
But resent trends also offer the possibility to high level languages.Furthermore,
there are library based solution which are optimized for a specific device.
17. Page 17
4.1. Hardware description language
Using a HDL is the most common approach to configure a FPGA. There
are two dominating languages, VHDL and Verilog. Both languages have the powe
of international standards and working groups behind and are similar powerful.
VHDL was developed in the 1980s.
Verilog was originally a C-like programming language to model hardware and late
became IEEE standard like VHDL. The languages support different levels of
abstraction, but mostconfigurations are done at the register transfer level (RTL).
The design resembles soft development more than hardware development, but
there are big differences. Software programs have a sequential execution model
and the correctness of the program depends on the sequential executed commands.
Decision points are very common. Furthermore, programmer does not have to care
about data flow between registers and memory.
Hardware designs consists of several block of hardware running in parallel. The
designer tries to avoid decision points, because of performance reasons. The wires
for data movement have to be explicitly written on the FPGA.
4.2. High level language
There are also approaches using high level languages that make designing FPGA
application more alike software development.
SystemC is a C++ library that allows to specify and simulate hardware processes
using a C++ syntax.Handel-C is an extended subset of ANSI C that allows
developer to specify their designs with C. It can be synthesized directly for
implementation on FPGAs.WithAccelchip it is possible to generate VHDL or
Verilog code block for common MATLAB DSP functions.
18. Page 18
5. Modern Development Of FPGA
Modern FPGAs have additional units that make the design of applications easier
and more efficient. Small memories and arithmetic units are difficult to implement
on CLBs. Therefore modern FPGAs provide embedded memories and embedded
logic blocks for arithmetic calculations. The most common arithmetic calculation
is the multiplication, but many other operations can be provided.
The advantage of embedded logic blocks are better speed and space. Additionally
embedded memories are easier to interface than extern memories. DSP
applications are often good targets for implementation on FPGA. Thus
manufacturer add embedded block to be useful for implementing DSP functions,
e.g. multipliers.
The Xilinx 4 family has support for additional operations configured by
the designer and implemented by CLBs with th auxiliary processing unit (APU)
interface.
In contrast to embedded processors, soft cores are build directly on the FPGA
fabric. The advantages are that they are configurable and the clock can be the same
as that of the FPGA. Furthermore, soft processor cores are easier to interface. The
big disadvantage is the slower clock rate.
5.1 The Xilinx Virtex-6 FPGA family
Virtex-6 the newest FPGA family from Xilinx. It is divided into the LXT, SXT and
HXT sub-family.Each sub-family contains a different ratio of features to address
the needs of many logic designs:
• Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity
19. Page 19
• Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial
connectivity
• Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity
CLBs possess a LUT which can be configured as one 6-input LUT or two 5-input
LUTs. The LUT also can be used as 64 bit RAM or 2 32 bit RAMs.
Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each
storing 36 Kbits. Each block RAM has two completely independent ports that
share nothing but the stored data.
All Virtex-6 FPGAs have many dedicated, full-custom, low-power DSP slices
combining high speed with small size, while retaining system design flexibility.
Each DSP48E1 slice fundamentally consists of a dedicated 25 18 bit two’s
complement multiplier and a 48-bit accumulator, both capable of operating at 600
MHz.
Every FPGA of the family contains a System Monitor circuit providing thermal
and power supply status information. Sensor outputs are digitized by a 10-bit
analog-to-digital converter (ADC). This fully tested ADC can also be used to
digitize up to 17 external analog input channels.
All but one Virtex-6 device has between 8 to 72 gigabit transceiver circuits. Each
GTX transceiver is a combined transmitter and receiver capable of operating
at a data rate between 155 Mb/s and 6.5 Gb/s. An integrated Ethernet MAC blockis
easily connected to the FPGA logic, the GTX transceivers,and the
SelectIOresources.All but one FPGAs of the Virtex-6
6. FPGA in Comparison To Other logic Devices
Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays,
even for wide input functions. Use CPLDs for small designs, where "instant-on",
20. Page 20
fast and wide decoding, ultra-low idle power consumption, and design security
are important (e.g., in battery-operated equipment).
Security: In CPLD once programmed, the design can be locked and thus
made secure. Since the configuration bitstream must be reloaded every time
power is re-applied, design security in FPGA is an issue.
Power: The high static (idle) power consumption prohibits use of CPLD in
battery-operated equipment. FPGA idle power consumption is reasonably low,
although it is sharply increasing in the newest families.
Design flexibility: FPGAs offer more logic flexibility and more
sophisticated system features than CPLDs: clock management, on-chip RAM,
DSP functions, (multipliers), and even on-chip microprocessors and Multi-
Gigabit Transceivers.These benefits and opportunities of dynamic
reconfiguration, even in the end-user system, are an important advantage.
7.Applications
Applications of FPGAs include digital signal processing, software-defined radio,
ASIC prototyping, medical imaging,computer vision, speech recognition,
cryptography, bioinformatics, computer hardware emulation,radio astronomy,
metal detection and a growing range of other areas.
7.1. FPGAs for Space Applications
21. Page 21
Dedicated to providing FPGAstha meet the stringent radiation and quality
requirements of space applications,Actel is the world’s leading supplier of
radiationhardened and radiationtolerant FPGAs. Over the last six years, Actel
devices have been on board more than 100 launches and have been accepted for
flight-critical applications on over 250 satellites.
Actel continues its commitment to the space community with the RTSX-SU and
RTAX-S/SL FPGA families. Designed specifically for space, the RTSX-SU and
RTAX-S/SL products are built on a foundation of hardened latches, eliminating the
need for softwaregeneratedtriple-module redundancy (TMR) or other single-
eventupset (SEU) mitigation techniques.
Xilinxhas increased the radiationhardened specification of its space grade
Virtex-5QV FPGA which is available with greater than 1Mrad(Si) total ionising
dose (TID) capabilities NASA sponsored Jet Propulsion
Laboratory and the University of Michigan will be the first to fly a
production Virtex-5QV FPGA.
The FPGAs are designed and tested to provide protection against SEU,total
immunity to single-event latchup (SEL), high tolerance to TID, as wellas data path
protection from single-event transients (SET).
For example, the Virtex-5QV FPGA configuration memory provides nearly
1,000 times the SEU hardness of the standard cell latches in the
commercial device, while configuration control logic and the JTAG
controller have been hardened with embedded triple module redundancy.
22. Page 22
This level of rad-hard performance positions FPGAs as an alternative to
space system designs based on one-time-programmable (OTP) devices or
Asics.
Virtex-5QV FPGAsare built on a second-generation ASMBL columnbased
architecture and integrate many of the same hard-IP system-level
blocks, such as 36kbit/18kbit block RAM/FIFOs, second generation 25x18
DSP slices, power-optimized high-speed serial transceiver blocks and PCI
Express compliant blocks.
The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices
supporting fixed and floating point operations, and 836 user I/Os
programmable to more than 30 different standards for applications and
ease of interfacing to a wide variety of system components.
Fig.Virtex-5QV FPGA
7.2. FGPA-Based Development for Defense and Aerospace
Applications
FPGA-Based COTS Boards
FPGA-based C OTS boards targeted to the defense/aerospace market often share
certain common elements.
23. Page 23
For example, they all provide one or more high-density, high-performance FPGAs,
high-speed serial I/O andhigh-performance memory.
Systems engineers evaluating FPGA boards must address certain challenges. These
include how to add their algorithms to the FPGA and how to simulate the design at
the system level to ensure that these algorithms work. Because FPGA development
can be costly, engineers also must evaluate whether their approach will save time
and money and if the resulting solution will be robust and reliable.
To understand the importance of design tools, it is useful to consider how data is
handled by an FPGA board.
In a typical application, data comes in via a high-speed serial interface and is
stored in SDRAM. This data is then pulled out of SDRAM by the end application
and processed via the customer’s algorithm. Intermediate results are stored in
internal or external SRAM and the final result is decimated to a lower data rate.
The FPGA Developers Kit
For DDR SDRAMs, FPGA designers must confront the challenges of aligning data
and data strobes, tight timingconstraints, signal integrity issues and simultaneously
switching output (SSO) noise. In addition, certaindesign issues can prolong design
cycles or force them to accept reduced performance.
To make matters worse, all of these hurdles become more pronounced at high
frequencies. On a read of datafrom SDRAM, the data is valid for only two to three
24. Page 24
nanoseconds. Significant effort is required to latch it reliably inside the FPGA and
then synchronize it with the rest of the logic there.
The FPGA designer is thus faced with significant challenges that may take several
man-months to complete, but that can be solved by using the IP in some FPGA
developers kits.In the ideal FPGA developers kit, all of the high-speed IP provided
is fixed to certain regions within the FPGA.This is done to ensure that all critical
paths meet timing, as well as to confine the overall IP designto a small region of
the chip to minimize logic resources.
Fig.FPGA Developers Kit Spartan-6
8. Future Scope Of FPGA Technology
When people think “summer,” visions of a slower pace, time off and less stress come to
mind. In many industries summer is indeed a time when business slows
downMeanwhile, summer for us at COTS Journal is the time when we hold important
planning meetings where we strategize about the upcoming year—deciding what
25. Page 25
technology topics will be important in the next calendar year and how to best cover
them.
It’s when we start putting together our editorial calendar for the following year.
As we looked ahead to where military electronics and embedded systems technology is
moving, over and over again the role of FPGAs kept cropping up.
In a recent study conducted by VDC Research, over one third of the total respondents
who answered that they were considering or already using FPGAs were
military/aerospace respondents. FPGAs have become a game changer as an enabler in
key compute-intensive military applications areas,
On the application side, FPGAs have had the most impact in radar/SIGINT, UAV
payloads and tactical military radios. Modern radar systems are operating over an ever
increasing frequency range. Analog conversion technology—both A/D and D/A
converters—is also feeding the radar needs of the military.
High-end military data acquisition is yet another area where FPGAs are playing a
central role. Military system designers face serious challenges when trying to move
signal data in ever-increasing volumes.
Importance of FPGAs is by no means a new phenomenon in military electronics. In a
way, the increasing role of FPGAs is in keeping with the idea that the definition of
“system” has changed. A system once meant simply a rack of board-level systems. Now
that same functionality can be incorporated in a few FPGAs. But as we look into
our crystal ball at the year ahead, they seem to be headed for a new plateau. So, while
you won’t necessarily see the word “FPGA” in every section topic of our upcoming 2010
Editorial Calendar, rest assured that this critical technology area will somehow get
weaved into a majority of them
9. Major Manufacturers
Xilinx and Altera are the current FPGA market leaders and long-time industry
rivals.Together, they control over 80 percent of the market.
Both Xilinx and Altera provide free Windows and Linux design software which
provides limited sets of devices.
26. Page 26
Other competitors include Lattice Semiconductor (SRAM based with integrated
configuration Flash, instant-on, low power, live reconfiguration), Actel (now
Microsemi, antifuse, flash-based, mixed-signal), SiliconBlue
Technologies (extremely low power SRAM-based FPGAs with optional integrated
nonvolatile configuration memory; acquired by Lattice in 2011),
In March 2010, Tabula announced their FPGA technology that uses time-
multiplexed logic and interconnect that
claims potential cost savings for high-density applications.
10.CONCLUSION
27. Page 27
We have presented a survey of field-programmable devices, describing the basic
technology that
provides the programmability and a description of many of the architectures in the
current marketplace.
We believe that over time programmable logic will become the dominant form of
digital logic
design and implementation. Their ease of access, principally through the low cost
of the devices,
makes them attractive to small firms and small parts of large companies. The fast
manufacturing
turn-around they provide is an essential element of success in the market. As
architecture and
CAD tools improve, the disadvantages of FPDs compared to Mask-Programmed
Gate Arrays will
lessen, and programmable devices will dominate.
"To improve affordability and flexibility of our space systems, we are
currently engaged in substantive efforts to insert space qualified FPGA
reconfigurable technology into future missions," said Craig Purcell, (advanced
global comms programme director at Lockheed Martin Space Systems).
11. References
1. Wisniewski, Remigiusz (2009). Synthesis of compositional microprogram
control units forprogrammabledevices.ZielonaGóra: University of
ZielonaGóra. pp. 153. ISBN 978-83-7481-293-1.
28. Page 28
2. FPGA Architecture for the Challenge
(http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html)Peter
Clarke, EE Times, "Xilinx, ASIC Vendors Talk Licensing
3. (http://www.eetimes.com/story/OEG20010622S0091)." June 22, 2001.
Retrieved February 10, 2009.
4. Funding Universe. ―Xilinx, Inc.
(http://www.fundinguniverse.com/company-histories/Xilinx-Inc-
Company-History.html) ‖ Retrieved January 15, 2009.
5. Press Release, "Xilinx Co-Founder Ross Freeman Honored as 2009 National
Inventors Hall of Fame Inductefor Invention of FPGA
(http://press.xilinx.com/phoenix.zhtml?c=212763&p=irolnewsArticle&I
D=1255523&highlight) "
6. Cheung, Ken, FPGA Blog. "Xilinx Extensible Processing Platform for
Embedded Systems
7. Leibson, Steve, Design-Reuse. "Xilinx redefines the high-end
microcontroller with its ARM-based Extensibl
8. Processing Platform - Part 1
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basedextensible-processing-platform.html) ."May. 03, 2010.
9. http://www.xilinx.com/support/documentation/user_guides/ug070.pdf
10.http://www.electronicsweekly.com/articles/04/08/2011/51605/xilinx-
prepares-fpgas-for-space-travel.htm