1) Flip-flops are basic memory elements that store one bit of information as a 1 or 0. Common types include RS, D, JK, and T flip-flops. 2) Registers are groups of flip-flops that can store multiple bits and perform data processing. Data is loaded into registers by transferring new information during a clock pulse. 3) Master-slave JK flip-flops prevent racing conditions by using two flip-flops triggered on opposite clock edges, with the slave output following the master.

1. SOFT SKILLS AND PERSONALITY DEVELOPMENT
TOPIC:FLIP-FLOPS AND REGISTERS
SUBMITTED BY
MOHAMMAD AZHAR UD DIN
ROLL NO:13YYSB6009

2. FLIP FLOPS
- Flip flop is the basic memory element in a digital computer.
It is used to store one
bit of information with 0 or 1. It is also called the Binary or
Toggle.
- Important characteristics of flip – flops are:
1) It is bistable device , has only two stable state 0 and 1.
2) The flip- flops has two Outputs . One output is the
complement of the other.

3. TYPES OF FLIP – FLOPS ARE:-
 RS FLIP – FLOP(RESET – SET FLIP –
FLOP).
 D FLIP – FLOP.
 JK FLIP – FLOP.
 MASTER SLAVE JK FLIP – FLOP.

4. RS FLIP FLOP
• It has inputs S(Reset), and C(clock). It has an output Q and a complemented
output Q’.
WORKING OF RS Flip-Flop
i) It both S and R are 0 during the clock transaction. The output does not
change.
ii) If S = 1 and R = 0 , the output Q is set 1.
iii) Is S=0 and R=1, the output is cleared to 0.
If both S and R are 1, the output is unpredictable , it may be 0 or 1.
Q
Q’
Set
clock
reset
S R Q(t+1) Comments
0 0 Q(t) No change
0 1 1 Clear or Reset to 0
1 0 1 Set to 1
1 1 ? Indeterminate

5. D- FLIP FLOP
•The D flip-flop is a flip- flop with a single data input and a clock
input C, it is called as Data flip-flop or Delay Flip –flop . The data at
D input is delayed by one clock Pulse before it gets to the output Q.
•Working of D Flip- Flop:
•Front the table , the next state Q( t + l) is determined Front the D
input. The relationship can be expressed by a characteristics
equation Q( t +l)=D.
Data
Clock
Q
Q’
Set
Clear/Reset
D Q(t +1)
0
1
0
1

6. JK FLIP -FLOP
. It is versatile and widely used type of flip flop . The j and k
designation for the input have no known signification
Working of JK Flip – Flip
i) When J and K inputs are both 0 the flip – flop is said to be in the
Hold state . There is no change.
ii) When j=0 and k=1,the flip flop is cleared to 0.
iii) When j=1 and k=0 the flip flop is cleared to 1.
J
k
Q
Q’
c
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t) (no change)
0 (reset to 0)
1 (set to 1)
Q’(t)

7. T FLIP -FLOP
. It is also known as Toggle Flip –Flop. The toggle mode of
operation JK is used as T flip flop.
Working of T Flip Flop
I)When T=0,clock transition does not change the state of flip
flop.
ii) When T=1,a clock transition complement the state of the
flip –flop.
Q
Q’
T
T Q n+1
0
1
Q n
Q’ n

8. Master Slave JK Flip Flop
Master slave flip flop consists of flip-flops.
The first is the master , which responds to the positive edges of clock . The
second is the slave , which responds to the negative edge of the clock . The
output changes only during the negative edge transition of the clock.
This helps in avoiding racing condition in JK flip flop where it can be
triggered only once within clock.
Since the output of the second flip flop follows that of the first JK flip-flop ,
the names Master and slave are used.
Set
Clock
Reset
Q
Q’
J
K
CLOCK
Q
Q’
J
K
CLOCK
Q
Q’
Master flip flop Slave flip flop

9. REGISTERS
A register is a group of flip flop with each flip – flop capable of
storing one bit of information .A register may have combination
gates that perform certain data processing tasks in addition to flip
–flop and gates that of registers are available ,consists only flip-
flop.
.Register Load:
o the transfer new information into register
is called “Loading the Register”.
D
C
Q
R
D
C
Q
R
D
C
Q
R
D
C
R
Q
D0D1D2D3
Q0Q1Q3 Q2
CLR
CLK

10. REGISTER WITH PARALLEL LOAD
The C input receive clock pulses all the time
The buffer gate in the clock input reduces the power requirement from
the clock generator.
The load input in the register determines the action to be taken with
each clock pulse, the D input determines the next state of the output .To
leave the output unchanged ,it is necessary to make the D input equal to
the present value of the outputs.
D
C
Q D
C
Q D
C
Q D
C
Q
INP
OUT
CLOC
K