This document defines sequential logic circuits and differentiates them from combinational logic circuits. It describes flip-flops, including SR and T flip-flops. It provides details on building SR and T flip-flops using logic gates, and includes their symbols and truth tables. The document focuses on the T flip-flop, providing its circuit diagram, explaining its toggle function, and including timing diagrams to demonstrate its behavior over multiple clock cycles.

1. Sequential
logic circuits
Combinational logic circuit
Sequential logic circuit
Flip-flop
Build flip-flop using logic gates
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2. Objectives:
• Define sequential logic circuit.
• Differentiate between combinational logic circuit and
sequential logic circuit.
• Describe flip - flop.
• Identify various types of flip-flops.
• Build SR and T flip – flop using logic gates.
• Draw the symbol and truth table of SR and T flip – flop.
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3. T Flip-Flop
Identify various types of flip-flops.
Build SR and T flip – flop using logic gates.
Draw the symbol and truth table of SR and T flip – flop.
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4. T Flip-Flop
Symbol:
Circuit Logic Symbol
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T
Q
Q'
CLK

5. T Flip-Flop
• The Toggle (T) Flip-Flop has two inputs
• One Clock signal input (Ck/ CLK) --- denoted by the small
arrowhead
• Toggle (T)
• We should provide only one input to the flip – flop called
Trigger input or Toggle input (T). Then the flip – flop acts as
a Toggle switch. Toggling means ‘Changing the next state
output to complement of the present state output’.
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6. T Flip-Flop
Truth Table:
• The T input controls the state change
• When the input T = 0 (‘LOW’), the state does not
change,
i.e. the T flip-flop holds its previous value.
• When the input T = 1, the state changes (‘toggles’)
following an active clock edge.
• Truth table of positive edge-triggered T flip-flop:
T CLK Q(t+1) Comments
0  Q(t) No change
1  Q(t)' Toggle 6
 = clock transition LOW to HIGH

7. Clock
• Flip-flops: synchronous bistable devices.
• Output changes state at a specified point on a
triggering input called the clock.
• Change state either at the positive edge (rising edge) or
at the negative edge (falling edge) of the clock signal.
Positive
edges
Negative edges
Clock signal
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8. T Flip-Flop
• Flip-flops are digital logic circuits that can be in one
of two states.
• Flip-flops maintain their state indefinitely until an
input pulse called a trigger is received.
• When a trigger is received, the flip-flop outputs
change state according to defined rules and remain in
those states until another trigger is received.
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9. T Flip-Flop
• T flip-flop is an edge triggered device i.e. the low to
high or high to low transitions on a clock signal of
narrow triggers that is provided as input will cause
the change in output state of flip-flop.
• The T-type Flip-Flop changes its states with every
clocked pulse and hence it is called as Toggle (T) Flip
Flop.
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10. T Flip-Flop
• The T flip flop has only the Toggle and Hold
Operation.
• In Toggle mode operation, the output will toggle
from 1 to 0 or vice versa.
• When the clock triggers, the value remembered by
the flip-flop either toggles or remains the same
depending on whether the T input is 1 or 0.
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11. SR NOR gate latch
Truth Table:
T Q
(current state)
Qnext
(next state)
0 0 0 Hold state
0 1 1 Hold state
1 0 1 Toggle
1 1 0 Toggle
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• The output of Q and NOT Q will not change (despite
making changes to the inputs) in a clocked flip-flop until
receiving a signal from the clock.

12. T-type Flip-Flop
Timing Diagram
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• Example: Determine the output of PGT T flip-flop for the given
input waveforms with the Q initially 0.

13. T-type Flip-Flop
Timing Diagram
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• Exercise 2: Determine the output
of NGT T flip-flop for the given
input waveforms in which Q
initially 0.
• Exercise 1: Determine the output of
PGT T flip-flop for the given input
waveforms in which Q initially 0.