The document discusses the evolution of MOSFET devices as channel lengths have decreased. Conventional bulk MOSFETs face physical limits controlling doping density, short channel effects, and gate oxide thinning. Alternative structures like partially depleted (PD) and fully depleted (FD) silicon-on-insulator (SOI) devices have emerged to extend scaling. PD SOI was initially adopted due to processing similarities to bulk devices. It offers advantages like reduced junction capacitance and dynamic threshold switching but requires addressing the floating body effect and hysteretic threshold variations.

1. Definition
Since the fabricationof MOSFET,the minimumchannel lengthhasbeenshrinkingcontinuously.The
motivationbehindthisdecreasehasbeenanincreasinginterestinhigh-speeddevicesandinverylarge-
scale integratedcircuits.The sustainedscalingof conventional bulkdevice requiresinnovationsto
circumventthe barriersof fundamental physicsconstrainingthe conventional MOSFETdevice structure.
The limitsmostoftencitedare control of the densityandlocationof dopantsprovidinghighIon/I off
ratioand finite subthresholdslope andquantum-mechanical tunnelingof carriersthroughthingate
fromdrain to source andfrom drainto body.
The channel depletionwidthmustscale withthe channel lengthtocontainthe off-stateleakageIoff.
Thisleads to highdopingconcentration,whichdegrade the carriermobilityandcausesjunctionedge
leakage due totunneling.Furthermore,the dopantprofile control,intermsof depthandsteepness,
becomesmuchmore difficult.The gate oxide thicknesstox mustalsoscale withthe channel lengthto
maintaingate control,properthresholdvoltageVTandperformance.The thinningof the gate dielectric
resultsingate tunnelingleakage,degradingthe circuitperformance,powerandnoise margin.
Alternativedevice structuresbasedonsilicon-on-insulator(SOI) technologyhave emergedasan
effectivemeansof extendingMOSscalingbeyondbulklimitsformainstreamhigh-performanceorlow-
powerapplications.Partiallydepleted(PD) SOIwasthe firstSOItechnologyintroducedforhigh-
performance microprocessorapplications.The ultra-thin-bodyfullydepleted(FD) SOIandthe non-
planarFinFETdevice structurespromise tobe the potential "future"technology/device choices.Inthese
device structures,the short-channel effectiscontrolledbygeometry,andthe thinSi filmlimitsthe off-
state leakage.Foreffective suppressionof the off-stateleakage,the thicknessof the Si filmmustbe less
than one quarterof the channel length.The desiredVTisachievedbymanipulatingthe gate work
function,suchas the use of midgapmaterial or poly-SiGe.Concurrently,material enhancements,suchas
the use of a) high-kgate material andb) strainedSi channel formobilityandcurrentdrive improvement,
have beenactivelypursued.As scalingapproachesmultiple physical limitsandasnew device structures
and materialsare introduced,unique andnew circuitdesignissuescontinuetobe presented.Inthis
article,we reviewthe designchallengesof these emergingtechnologieswithparticularemphasisonthe
implicationsandimpactsof individual device scalingelementsandunique device structuresonthe
circuitdesign.We focuson the planardevice structures,fromcontinuousscalingof PDSOIto FD SOI,
and newmaterialssuchasstrained-Si channelandhigh-kgate dielectric.
Partially Depleted [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for
high-performance applications, primarily due to device and processing similarities to
bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except forthe addition of a
buried oxide ("BOX") layer. The active Si film thickness is larger than the channel
depletion width, thus leaving a quasi-neutral "floating" body region underneath the
channel. The V T of the device is completely decoupled from the Si film thickness,

2. and the doping profiles can be tailored for any desired VT. The device offers several
advantages forperformance/ power improvement:
1) Reduced junction capacitance,
2) Lower average threshold due to positive V BS during switching.
3) Dynamic loading effects,in which the load device tends to be in high VT state
during switching The performance comes at the cost of some design complexity
resulting from the floating body of the device, such as
1) Parasitic bipolar effect and
2) Hysteretic VT variation.
1) Reduced junction capacitance,
2) Lower average threshold due to positive V BS during switching.
3) Dynamic loading effects, in which the load device tends to be in high VT state during
switching The performance comes at the cost of some design complexity resulting from the
floating body of the device, such as
1) Parasitic bipolar effect and
2) Hysteretic VT variation.