This document discusses FinFET technology. It begins with an introduction to FinFETs, explaining that they are a type of double-gate CMOS that offers advantages over traditional CMOS for scaling to short gate lengths. It then discusses why FinFET technology is needed as traditional CMOS scaling faces challenges from subthreshold and gate leakage. It provides details on double-gate FET structure and operation, including how it controls short-channel effects better than single-gate FETs. It also covers FinFET features, applications, challenges and concludes that FinFETs can help continue CMOS scaling if key issues like fin patterning and gate work functions are addressed.

1. Submitted by
K.Navya Tejaswini
17304013

2. CONTENTS
 Introduction to FinFET
 Why FinFET Technology?
 Double-Gate FET
 Double-Gate threshold voltage
 Double-Gate Taxonomy
 Type 1 planar DGFET
 Type 2 vertical DGFET
 Type 3 non planar FinFET
 The Double gate challenges
 Features of FinFET
 Future applications
 Challenges in future
 Conclusion
 References

3. INTRODUCTION TO FINFET
Innovative device architectures will be necessary to
continue the benefits that previously acquired through rote
scaling. Double-gate CMOS (DGCMOS) offers distinct
advantages for scaling to very short gate lengths. Furthermore,
adoption of gate dielectrics with permittivity substantially
greater than that of SiO2 (so-called “high-k materials”) may be
deferred if a DGCMOS architecture is employed.

4. Previously, serious structural challenges have made adoption of
DGCMOS architecture untenable. Recently, through use of the delta device,
now commonly referred to as the FinFET, significant advances in DGCMOS
device technology and performance have been demonstrated. Fabrication in
FinFET-DGCMOS is very close to that of conventional CMOS process, with
only minor disruptions, offering the potential for a rapid deployment to
manufacturing.
Planar product designs have been converted to FinFET–DGCMOS
without disruption to the physical area, thereby demonstrating its
compatibility with today’s planar CMOS design methodology and
automation techniques.

5. WHY FinFET TECHNOLOGY?
 CMOS technology scaling has traversed many anticipated
barriers over the past 20 years to rapidly progress from 2µm to
90 nm rules. Currently, two obstacles, namely sub threshold
and gate-dielectric leakages, have become the dominant barrier
for further CMOS scaling, even for highly leakage -tolerant
application such as microprocessors.

6. DOUBLE GATE FET
 Double-gate (DG) FETs, in which a second gate is added
opposite the traditional (first) gate, have better control over
short-channel effects [SCEs]. SCE limits the minimum channel
length at which an FET is electrically well behaved.
Figure :schematically illustrates the advantage of DG-FETs.

7. • As the channel length of an FET is reduced, the drain potential
begins to strongly influence the channel potential, leading to an inability
to shut off the channel current with the gate.
• This short -channel effect is mitigated by use of thin gate oxide and
thin depletion depth below the channel to the substrate, to shield the
channel from the drain.
• Gate oxide thickness has been reduced to the point where, at 90 nm
CMOS, the power drain from gate leakage is comparable to the power
used for switching of circuits.
• Thus, further reduction of the thickness would lead to unreasonable
power increases.

8. • In DG-FETs, the longitudinal electric field generated by the drain is better
screened from the source end of the channel due to proximity to the channel of the
second gate, resulting in reduced short -channel effects, in particular, reduced drain
induced- barrier lowering (DIBL) and improved subthreshold swing .
• Therefore, as CMOS scaling becomes limited by leakage currents,
DGCMOS offers the opportunity to proceed beyond the performance of single-
gate (SG) bulk-silicon or PDSOI CMOS.
• Both the DIBL and subthreshold swing for the DG device are dramatically
improved relative to those of the bulk-silicon counterpart.
• Decreasing the body doping concentration could improve the subthreshold
swing but degrade DIBL. Hence a compromise is necessary for the bulk-silicon
device design.

9. Figure : IDS Vs VGS
In Figure,the IDS–VGS characteristics of DG and SG FETs shows the steeper
turn on of the DG-FET, which results from the gate coupling advantage. This
property enables the use of lower threshold voltage for the DG-FET for a given off-
current. As a direct result, higher drive currents at lower power-supply voltages VDD
are attainable.

10. DOUBLE-GATE THRESHOLD
VOLTAGE
 The very thin silicon body associated with fully depleted
DG-FETs suggests that the centering of VT could be a
challenging proposition. Three basic techniques have
been explored by use of body doping, use of asymmetric
gate work function, and use of symmetric mid-gap work-
function gate-electrodes.

11. Adequate body doping can be achieved by directly doping the silicon
body or by use of ion implants introduced laterally from the gate edges,
or a combination of these two techniques.
One technique uniquely available to DG-FETs is the use of asymmetric
gates, where in the two gate electrodes are of materials of differing work
functions.
 Metal gates offer the possibility of centering threshold voltage with a
single work function for both gate electrodes without relying on body
doping.
Metal gates on DG-FETs, on the other hand, naturally achieve the VTs
in the vicinity of 0.2 V and good short channel characteristics.

12. DOUBLE-GATE TAXONOMY
 Numerous structures for DG-FETs have been proposed and
demonstrated. These structures may be classified into one of the
three basic categories.
Type I:The Planar DG-FET
This is a direct extension of a planar CMOS process with a
second, buried gate.
Figure : planar DG-FET.

13.  Type II:The Vertical DG-FET
Here the silicon body has been rotated to a vertical orientation on the silicon
wafer with the source and drain on the top and bottom boundaries of the body, and the
gates on either side.
Figure: Vertical DG-FET

14. Type III :Non Planar FinFET
In FinFET the silicon body has been rotated on its edge into a vertical
orientation so only the source and drain regions are placed horizontally about the
body, as in a conventional planar FET. Referred to as FinFETs as the silicon
resembles the dorsal fin of a fish.
Figure : Non Planar DG-FET

15. DOUBLE GATE CHALLENGES
DG-FETs have been the subject of much research for over 20
years; hence, if DGCMOS offers significant advantage over SG
devices.
 The four major obstacles to DGCMOS are represented schematically.
 The first three issues are closely related to one another and consist of
1. definition of both gates to the same image size accurately
2. self-alignment of the source/drain regions to both top and bottom
gates
3. alignment of the two gates to one another.
These three goals are critical for short devices to provide high drive
current and low gate capacitance simultaneously.
4. The fourth obstacle is that of providing an area-efficient means of
connecting the two gates with a low-resistance path

16. FEATURES OF FINFET
 Finfet consists of a vertical Si fin controlled by self-aligned
double gate. Main Features of Finfet are
1) Ultrathin Si fin for suppression of short channel effects
2) Raised source/drain to reduce parasitic resistance and improve
current drive
3) Gate-last process with low T, high k gate dielectrics
4) Symmetric gates yield great performance, but can built
asymmetric gates that target VT.

17. FUTURE APPLICATIONS
SRAM
 Device variability is a big concern for further scaling of
planar bulk SRAM.FinFET has a chance to break through
the barrier by its good SCE controllability and its good
matching.
ANALOG
 The good SCE control in FinFETs is beneficial not only
for digital but also for analog applications. By optimizing
the process, FinFETs show higher voltage gain and higher
transconductance than planar FETs.

18. CHALLENGES IN FUTURE
 Fin PATTERNING
Although finFETs have an intrinsically small variability
due to the good channel potential control by the double gate
structure and the low channel dopant concentration, their
variability is dramatically influenced by fin/gate patterning.
And the patterning becomes more difficult in the dense finFET
structures such as scaled SRAMs. Therefore, the precise
fin/patterning control is a key for finFET future.

19. oGATE PATTERNING
In the gate etch in finFETs, both the gate cd control and
the gate end of line control are important, especially dense
finFET patterns such as SRAM. The standard single
mask/single etch approach for the gate patterning can make the
gate cd on target but it suffers from the end of line shortening.

20. CONCLUSION
 Formation of ultrathin fin is critical for suppressing short channel effects.
This structure was fabricated by forming the SD before the gate, a
technique that may be needed for future high-k dielectric and metal- gate
technologies that cannot tolerate the high temperatures required for
S D formation.
 Further performance improvement is possible by using a thinner gate
dielectric and thinner spacers.
 Despite its double gate structure, the FinFET is similar to the
conventional MOSFET with regard to layout and fabrication.

21. o Issues such as gate work function engineering, high quality ultrathin
fin lithography and sourcedrain resistance need to be resolved and a high-
yield process flow needs to be established by process researchers before
FinFETs can be used in commercial ICs. Device researchers need to
understand and model quantum effects, and circuit design researchers need to
exploit the packing density afforded by the quasi-planar device to design
efficient architectures.

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