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Cmos process flow

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Cmos process flow

  1. 1. VLSI Fabrication Technology CMOS Technology
  2. 2. Examples of Simple CMOS Circuits +V +V IN1 PMOS IN2 OUTPUT OUTPUT INPUT NMOS GND GND An Inverter A NOR Gate
  3. 3. CMOS Process Flow D G D Sub Sub G S S G P+ S D N S N+ P+ N Well - PMOS Substrate D G P N+ P Well - NMOS Substrate P • Cross sectional view of final CMOS circuits
  4. 4. CMOS Process Flow Photoresist Si3N4 SiO2 Si, (100), P Type, 5-50 žcm • Substrate selection: moderately high resistivity, (100) orientation, P type, 25-50 Ohm-cm • Wafer cleaning, thermal oxidation (≈ 40 nm), nitride LPCVD deposition (≈ 80 nm), photoresist spinning and baking (≈ 0.5 - 1.0 µm).
  5. 5. CMOS Process Flow P • Mask #1 patterns the active areas. The nitride is dry etched.
  6. 6. CMOS Process Flow P • Field oxide is grown using a LOCOS process. Typically 90 min @ 1000 ˚C in H2O grows ≈ 0.5 µm.
  7. 7. CMOS Process Flow Boron P Implant P • Mask #2 blocks a B+ implant to form the wells for the NMOS devices. Typically 1013 cm-2 @ 150-200 KeV.
  8. 8. CMOS Process Flow Phosphorus N Implant P Implant P • Mask #3 blocks a P+ implant to form the wells for the PMOS devices. Typically 1013 cm-2 @ 300+ KeV.
  9. 9. CMOS Process Flow N Well P Well P • A high temperature drive-in produces the “final” well depths and repairs implant damage. Typically 4-6 hours @ 1000 ˚C - 1100 ˚C or equivalent Dt.
  10. 10. CMOS Process Flow Boron P N Well P Well P • Mask #4 is used to mask the PMOS devices. A VTH adjust implant is done on the NMOS devices, typically a 1-5 x 1012 cm-2 B+ implant @ 50 - 75 KeV.
  11. 11. CMOS Process Flow Arsenic N P N Well P Well P • Mask #5 is used to mask the NMOS devices. A VTH adjust implant is done on the PMOS devices, typically 1-5 x 1012 cm-2 As+ implant @ 75 - 100 KeV.
  12. 12. CMOS Process Flow N P N Well P Well P • The thin oxide over the active regions is stripped and a new gate oxide grown, typically 3 - 5 nm, which could be grown in 0.5 - 1 hrs @ 800 ˚C in O2.
  13. 13. CMOS Process Flow N P N Well P Well P • Polysilicon is deposited by LPCVD ( ≈ 0.5 µm). An unmasked P+ or As+ implant dopes the poly (typically 5 x 1015 cm-2) or In-Situ doping
  14. 14. CMOS Process Flow N P N Well P Well P • Mask #6 is used to protect the MOS gates. The poly is plasma etched using an anisotropic etch.
  15. 15. CMOS Process Flow Phosphorus P N N Im plant NW ell PW ell P • Mask #7 protects the PMOS devices. A P+ implant forms the LDD regions in the NMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).
  16. 16. CMOS Process Flow Boron N P P Im plan t N Im plan t NW ell PW ell P • Mask #8 protects the NMOS devices. A B+ implant forms the LDD regions in the PMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).
  17. 17. CMOS Process Flow N P P- Implant N- Implant N Well P Well P • Conformal layer of SiO2 is deposited (typically 0.5 µm).
  18. 18. CMOS Process Flow N P P- Implant N- Implant N Well P Well P • Anisotropic etching leaves “sidewall spacers” along the edges of the poly gates.
  19. 19. CMOS Process Flow Arsenic N P N+ Implant N Well P Well P • Mask #9 protects the PMOS devices, An As+ implant forms the NMOS source and drain regions (typically 2-4 x 1015 cm-2 @ 75 KeV). Growth of Screen oxide (10nm) to avoid channeling
  20. 20. CMOS Process Flow Boron N P P+ Implant N+ Implant N Well P Well P • Mask #10 protects the NMOS devices, A B+ implant forms the PMOS source and drain regions (typically 1-3 x 1015 cm-2 @ 50 KeV).
  21. 21. CMOS Process Flow P+ N N+ P+ N Well P N+ P Well P • A final high temperature anneal drives-in the junctions and repairs implant damage (typically 30 min @ 900˚C or 1 min RTA @ 1000˚C.
  22. 22. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • An unmasked oxide etch allows contacts to Si and poly regions.
  23. 23. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • Ti is deposited by sputtering (typically 100 nm).
  24. 24. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • The Ti is reacted in an N2 ambient, forming TiSi2 and TiN (typically 1 min @ 600 - 700 ˚C).
  25. 25. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • Mask #11 is used to etch the TiN, forming local interconnects.
  26. 26. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • A conformal layer of SiO2 is deposited by LPCVD (typically 1 µm). PSG/BPSG
  27. 27. CMOS Process Flow P+ N P+ N+ N Well P P Well P • CMP is used to planarize the wafer surface. N+
  28. 28. CMOS Process Flow P+ N P+ N+ N Well P P Well P • Mask #12 is used to define the contact holes. The SiO2 is etched. N+
  29. 29. CMOS Process Flow TiN W P+ N P+ N+ N Well P N+ P Well P • A thin TiN barrier layer is deposited by sputtering (typically a few tens of nm), followed by W CVD deposition.
  30. 30. CMOS Process Flow • CMP is used to planarize the wafer surface, completing the damascene process.
  31. 31. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • Al is deposited on the wafer by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it.
  32. 32. CMOS Process Flow P+ N P+ N+ N Well P N+ P Well P • Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16. • This completes the CMOS structure.
  33. 33. Unit Processes  Crystal Growth  Chemical Processing  Oxidation  Diffusion Clean  Photolithography Rooms  Ion Implantation  Chemical Vapour Deposition  Dry Etching  Metalization  Inspection and Testing  Packaging The above steps will repeat, not in the order specified above, but, as and when required depending on device complexity and target structure.
  34. 34. Summary • An initial discussion on the CMOS process flow provides an introduction to the modern VLSI technology. • It provides a perspective on how individual technologies like oxidation and ion implantation are actually used. • There are many variations on CMOS process flows used in the industry. • The process described here is intended to be representative, although it is simplified compared to many current process flows.
  35. 35. Summary • Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologies, their actual use is very much complicated by the fact that IC manufacturing consists of many sequential steps, each of which must integrate together to make the whole process flow work in manufacturing.
  36. 36. Modern CMOS Technology • We will describe a modern CMOS process flow. • In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated in the next slide. • Typical CMOS technologies in manufacturing today add additional steps to implement multiple device VTH, TFT devices for loads in SRAMs, capacitors for DRAMs etc. • Process described here will require 16 masks (through metal 2) and > 100 process steps. • There are many possible variations on CMOS process flow e.g. Device Isolation using Field Oxide or Shallow Trench Formation.

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