This document describes the design of a speed optimized analog-to-digital converter (ADC) using VHDL. It begins with background on ADCs and their components. A state transition diagram is drawn based on the ADC timing diagram and implemented in VHDL. The design is simulated using ModelSim and synthesized using Xilinx tools. Simulation waveforms show the ADC operating correctly. The new control method allows for higher clock frequencies and simpler programming compared to previous designs.