This document provides a summary of a progress report on the design of a 3-bit flash analog-to-digital converter (ADC). It describes the architecture and design of a comparator, which acts as a 1-bit ADC, and a 3-bit flash ADC. It also discusses characterization of the ADC's DC performance by measuring differential nonlinearity and integral nonlinearity from histograms. The document covers comparator design techniques, reference voltage generation using diode-connected transistors, and layout of the 3-bit flash ADC.

1. Three Bit Flash ADC Design
A First Year Progress Report Submitted
In partial fulfillment of the requirements
for the award of the degree of
Doctor of Philosophy
by
ANKIT SHIVHARE
Roll No. 13AT92R03
Under the Guidance Of
PROF. AMIT PATRA
ELECTRICAL ENGINEERING DEPARTMENT
INDIAN INSTITUTE OF TECHNOLOGY
KHARAGPUR -721302, INDIA.
APRIL, 2015

2. 2
TABLE OF CONTENTS
CHAPTER-1 INTRODUCTION ……………………… 1
ADC Architecture Overview ……………………… 3
1.1 Pipeline ADC ……………………… 4
1.2 SAR ADC ……………………… 5
1.3 Delta-Sigma ADC ……………………… 6
1.4 Flash ADC ……………………… 8
CHAPTER-2 COMPARATOR/ 1 BIT ADC ……………….. 12
CHAPTER-3 FLASH/PARALLEL COMPARATOR
ADC DESIGN ……………………… 13
CHAPTER-4 CHARACTERIZATION OF ADC .………………… 15
CHAPTER-5 CONCLUSION AND FUTURE WORK ……….. 16
REFERENCES ………………………………………………..… 18

3. 3
LIST OF FIGURES
Figure
Number
Description Page No.
Figure-1 Basic Successive Approximation ADC
(Feedback Subtraction ADC)
6
Figure-2 Pipeline ADC with four 3-bit stages
(each stage resolves two bits)
7
Figure-3 First-Order Sigma-Delta ADC 8
Figure-4 Block Diagram of Flash ADC 9
Figure-5 Resolution VS Sampling Rate for
different types of ADC
10
Figure-6 Block Diagram of Comparator 12
Figure-7 Wide Swing Dynamic Comparator Schematic 13
Figure-8 Schematic of 3 Bit Flash ADC 15
Figure-9 Schematic on NAND gate 16
Figure-10 Layout of 3 Bit Flash ADC 17
Figure-11 Transient plot, Slow varying Ramp input
is applied to measure DC Characteristic of Flash ADC
19
Figure-12 DNL and INL Extracted from histogram DNL=±0.2
LSB, INL= 0.04 LSB
21
Figure-13 Test Circuit to measure AC Characteristic of 3 Bit
Flash ADC
24
Figure-14 Figure-14: FFT Plot schematic (excluding parasitic) for
fin=3.891KHz, fs=500 KHz, m= 127, N=16384, tsim=
32.168 ms , SINAD= 16.162 dB
25
Figure-15 Figure-15: FFT Plot including parasitic fin=3.891KHz,
fs=500 KHz, m= 127, N=16384, tsim= 32.168 ms ,
SINAD= 9.0107 dB
26
Figure-16 Figure-14: FFT Plot schematic (excluding parasitic) for
fin=3.891KHz, fs=500 KHz, m= 127, N=16384, tsim=
32.168 ms , SINAD= 16.162 dB
27

4. 4
LIST OF TABLES
Table Number Description Page No.
Table-1 Different Architecture of ADCs showing there
latency, speed and accuracy performance
11
Table-2 Functional Description of 1 Bit ADC/ Comparator 13
Table-3 W/L ratios for each block of Comparator 13
Table-4 W/L ratios of each block of 3 Bit Flash ADC 15

5. 5
CHAPTER-1
INTRODUCTION
In recent years, signal processing has gained ample significance making high
speed and low voltage analog to digital converters (ADC) inevitable in numerous
application.
Analog-to-Digital Converter (ADC)
An ADC converts real time analog signals into digital codes. An ADC has a
reference voltage or current against which the analog input is compared. The N-bit
digital output word indicates which fraction of the reference quantity Vref the
input quantity Vin is. The input-output transfer function is described by
Output-code, 𝑫𝒐𝒖𝒕 =
𝟐 𝑵 𝑽𝒊𝒏
𝑽𝒓𝒆𝒇
𝒐𝒓
𝟐 𝑵 𝑰𝒊𝒏
𝑰𝒓𝒆𝒇
---------- (1)
Where, N is the number of bits that can be resolved by the ADC, Vin or Iin
correspond to the input quantity.and Vref or Iref correspond to the reference value
against which the input will be compared. The resolution of an ADC is the number
of bits in the digital output code. Alternatively, it can be defined as the size of the
least significant bit (LSB). In a N-bit ADC, we will have 2 𝑁
possible levels. If the
full scale range of the ADC is FSR, then
𝟏 𝑳𝑺𝑩 =
𝑭𝑺𝑹
𝟐 𝑵 ---------- (2)
There are basic four types of ADC and each has its own intended applications.
Although with present market needs more and more combinations of ADCs have
been coined up. A brief review of four types of ADC is given.
(A)SAR ADC
(B)Pipeline ADC
(C)Delta-Sigma ADC
(D)Flash ADC

6. 6
(A) Successive Approximation ADC
The successive approximation ADC has been the mainstay of data acquisition
systems. Recent design improvements have extended the sampling frequency of
these ADCs into the megahertz region with 18 bit resolution. The basic successive
approximation ADC is shown in Figure 1. An N-bit conversion takes N steps.
Figure-1 Basic Successive Approximation ADC (Feedback Subtraction ADC)

7. 7
(B)Pipeline ADC Architecture
In schematic, the analog input, VIN, is first sampled and held steady by a sample-
and-hold (S&H), while the flash ADC in stage one quantizes it to three bits. The 3-
bit output is then fed to a 3-bit DAC, and the analog output is subtracted from the
input. This “residue” is then gained up by a factor of four and fed to the next stage
(Stage 2). This gained-up residue continues through the pipeline, providing three
bits per stage until it reaches the 4-bit flash ADC, which resolves the last 4 LSB
bits. Because the bits from each stage are determined at different points in time, all
the bits correspond to the sample are time-aligned with shift registers before being
fed to the digital-error-correction logic. Pipelining action results in high throughput
as each stage finishes processing a sample, determining the bits, and passing the
residue to the next stage, it can then start processing the next sample received from
the S&H embedded within each stage. Latency is encountered as each sample
needs to propagate through the entire pipeline before all its associated bits are
available for combining in the digital-error-correction logic.
Figure-2 Pipeline ADC with four 3-bit stages (each stage resolves two bits)

8. 8
(C) SIGMA DELTA ADC
Here, the integrator is constantly ramping up or down at node A. The output of the
comparator is fed back through a 1-bit DAC to the summing input. The negative
feedback loop from the comparator output through the 1-bit DAC to the summing
point will force the average dc voltage at node B equal to VIN. This implies that
the average DAC output voltage must equal the input voltage VIN. The average
DAC output voltage is controlled by the ones-density in the 1-bit data stream from
the comparator output. If input signal increases towards +Vref, the number of
“ones” in the serial bit stream increases, and the number of “zeros” decreases.
Similarly, as the signal goes negative towards –Vref, the number of “ones” in the
serial bit stream decreases, and the number of “zeros” increases. Thus, it can be
shown that the average value of the input voltage is contained in the serial bit
stream out of the comparator. The digital filter and decimator process the serial bit
stream and produce the final output data. [3]
Figure-3 First-Order Sigma-Delta ADC

9. 9
(D)Flash ADC
In this circuit analog voltage, Vo is applied simultaneously to a bank of comparators
with equally spaced threshold voltages (reference voltages VR1=V/8, VR2=2V/8,
etc.). This type of processing is called bin conversion, because the analog input is
sorted into a given voltage range or “voltage bin” determined by the threshold of
two adjacent comparators.
Conversion time is limited only by the speed of the comparator and of the priority
encoder. An obvious drawback of this technique is the complexity of the hardware.
The number of comparators needed is 2N
-1, where N is the desired number of bits.
Hence the number of comparators approximately doubles for each added bit. Also,
larger the N, the more complex is the priority encoder.
Figure-4 Block Diagram of Flash ADC

10. 10
Flash or Parallel Converters have the highest speed of any type of ADC. They use
one comparator per quantization level. Here, instead of using resistor for reference
voltage generation we have used diode connected PMOS transistors. MOS
transistors take considerably smaller area as compared to resistors in silicon, sizing
transistor is preferred compared to placing resistors. Also variation in length of
resistors creates more mis-match for reference voltage generation. The reference
voltage is divided into 2N
values, each of which is fed into a comparator. The input
voltage is compared with each reference value and results in a thermometer code at
the output of the comparators.
A thermometer code exhibits all zeros for each reference level if the value of Vin is
less than the value on the reference, and ones if Vin is greater than or equal to the
voltage on the reference.
RESOLUTION VS BANDWIDTH FOR DIFFERENT TYPES OF ADC
Figure-5 Resolution VS Sampling Rate for different types of ADC

11. 11
The figure illustrates ADCs purpose as per application requirements. Delta-Sigma
provides highest resolution but at cost of lower sampling rate. Flash ADC has
higher sampling rate but has poor resolution. Flash ADC but has distinctive
advantage of possessing high speed.
Architecture Latency Speed Accuracy
Flash Low High Low
SAR Low Low-medium Medium-high
Folding +
Interpolating
Low Medium-high Medium
Delta-sigma High Low High
Pipeline High Medium-high Medium-high
Table1: Different Architecture of ADCs showing there latency, speed and
accuracy performance

12. 12
CHAPTER-2 COMPARATOR/ 1 BIT ADC
The comparator can be thought of as a decision-making circuit. If the +,Vp, input
of the comparator is at a greater potential than the -,Vm, input, the output of the
comparator is at a logic 0.
𝑉𝑝 > 𝑉𝑚 𝑡ℎ𝑒 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 1
𝑉𝑝 < 𝑉𝑚 𝑡ℎ𝑒𝑛 𝑉𝑜𝑢𝑡 = 0 𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 0
A block diagram of a high –performance comparator is shown in Figure-6. A
Comparator is a one-bit ADC. The comparator consist of three stages: the input
preamplifier, a positive feedback or decision stage and an output buffer
Figure-6 Block Diagram of Comparator
A comparator whose outputs change on the rising or falling edge of a clock signal.
When clock is low, the inputs to the NAND SR latch are pulled high. The outputs
of the comparator don’t change. When clock goes high, the two inputs are
compared causing the output of the circuit to register which one is higher.

13. 13
Figure-7: Wide Swing Dynamic Comparator Schematic
Preamplifier and Differential Amplifier stage are clubbed together in
Preamplification stage. Both stages are required to reduce kickback noise resulting
due to positive feedback action in Decision circuit. Decision circuit is able to
discriminate mV level signals. The circuit uses positive feedback action from the
cross gate connection of latch transistors.
FUNCTIONAL DESCRIPTION
Pin Name Description
VDD Positive supply terminal, +1.8V
NON INVERTING
INPUT (VP)
Noninverting analog input of the differential input stage.
The NONINVERTING INPUT must be driven in
conjunction with the INVERTING INPUT.
INVERTING
INPUT (VM)
Inverting analog input of the differential input stage. The
INVERTING INPUT must be driven in conjunction with
the NON INVERTING INPUT.

14. 14
OUT One of two complementary outputs. OUT will be at logic
HIGH if the analog voltage at the NONINVERTING
INPUT(VP) is greater than the analog voltage at the
INVERTING INPUT(VM)
OUT_B One of two complementary outputs. OUT will be at logic
HIGH if the analog voltage at the INVERTING
INPUT(VM) is greater than the analog voltage at the
NONINVERTING INPUT(VP)
Table-2 Functional Description of 1 Bit ADC/ Comparator
CIRCUIT DESCRIPTION PMOS NMOS
BIAS CIRCUIT M12 10u/5u F=2 M11 5u/1u F=1
PREAMPLIFIER STAGE M214 10u/5u F=2
M215 10u/5u F=2
M211 20u/500n F=2
M212 20u/500n F=2
M213 20u/500n F=2
M226 30u/500n F=4
M227 30u/500n F=4
M228 30u/500n F=4
M229 10u/5u F=2
M230 10u/5u F=2
DIFFERENTIAL INPUT
AMPLIFIER
M34 10u/10u F=1
M35 20u/1u F=4
M36 20u/1u F=4
M31 10u/10u F=1
M32 2u/500n F=2
M33 2u/500n F=2
CLOCKED LATCH STAGE
LATCH
CLOCK
M45 5u/180n F=2
M46 5u/180n F=2
M47 20u/500n F=4
M48 20u/500n F=4
M41 10u/500n F=4
M42 10u/500n F=4
M43 2u/180n F=2
M44 2u/180n F=2
SR NAND MEMORY STAGE M55 240n/180n F=1
M56 240n/180n F=1
M57 240n/180n F=1
M58 240n/180n F=1
M51 240n/180n F=1
M52 240n/180n F=1
M53 240n/180n F=1
M54 240n/180n F=1
Table-3 W/L ratios for each block of Comparator

15. 15
CHAPTER-3
FLASH/PARALLEL COMPARATOR ADC DESIGN
Figure-8: Schematic of 3 Bit Flash ADC

16. 16
REFERENCE STAGE
PMOS NMOS
W/L=2u/1u F=2
Diode Connected
Stage
VBS=0
COMPARATOR STAGE Specified in Table1 Specified in Table1
NAND STAGE M0,1 W/L=2u/500n
F=2
M2,3 2u/500n F=2
THERMOMETER
ENCODER STAGE
W/L=2u/500n F=2 W/L=1u/10u F=1
Table -4 W/L ratios of each block of 3 Bit Flash ADC
Figure-9 Schematic on NAND gate

17. 17
Figure-10: Layout of 3 Bit Flash ADC

18. 18
CHAPTER-4
CHARACTERIZATION OF ADC
Using N bit analog-to-digital converter (ADC) does not necessarily mean that
system will have N bit accuracy. A system having an N bit ADC can have much
lower performance than expected. ADC specifications can lead to desired
performance of system. It also helps user to select right ADC for intended
application. Accuracy of the ADC is dependent on several key specs, which
include integral non linearity error (INL), offset and gain errors, and the accuracy
of the voltage reference, temperature effects, and AC performance. It is usually
wise to begin the ADC analysis by reviewing the DC performance, because ADCs
use a plethora of non-standardized test conditions for the AC performance, making
it easier to compare two ICs based on DC specifications. The DC performance will
in general be better than the AC performance.
DC Performance
1. Differential nonlinearity (DNL)
DNL reveals how far a code is from a neighboring code. The distance is
measured as a change in input-voltage magnitude and then converted to LSBs.
The key performance for an ADC is the claim “no missing codes.” This means
that, as the input voltage is swept over its range, all output code combinations will
appear at the converter output. A DNL error of < ±1 LSB guarantees no missing
codes.
𝐷𝑁𝐿(𝑛) =
𝑉𝑎𝑐𝑡𝑢𝑎𝑙(𝑛) − 𝑉𝑎𝑐𝑡𝑢𝑎𝑙(𝑛 − 1)
𝐿𝑆𝐵
− 1
Where 𝑉𝑎𝑐𝑡𝑢𝑎𝑙(𝑛) is the voltage corresponding to input at which the ADC
transitions from code (n-1) to (n)
2. Integral nonlinearity (INL)
INL is defined as the integral of the DNL errors, so good INL
guarantees good DNL. The INL error tells how far away from the ideal

19. 19
transfer-function value the measured converter result is. It is defined as
follows-
𝐼𝑁𝐿(𝑛) =
𝑉𝑎𝑐𝑡𝑢𝑎𝑙(𝑛) − 𝑉𝑖𝑑𝑒𝑎𝑙(𝑛)
𝐿𝑆𝐵
HISTOGRAM TESTING / CODE DENSITY TEST
The histogram test approach helps determine non linearity parameters such as
differential and integral nonlinearities (INL and DNL) in data converters. DNL is
derived directly from total occurrences of each code @ the output of the ADC [2].
ADC sampling rate, fs=100KHz, Ts=10µs, 1LSB= 10mV. For 0.01LSB
measurement resolution: n=100 samples/code. Thus, Ramp duration per
code:=100×10µsec=1msec. Ramp slope=10mV/msec.
Figure-11: Transient plot, Slow varying Ramp input is applied to meaasure
DC Characteristic of Flash ADC

20. 20
Steps for DNL and INL calculation:
1. Remove “Over-range bins” (0 and full scale)
2. Compute average count/bin (600/6=100 in this case)
3. Normalize: Divide histogram by average count/bin. Ideal bins have exactly
the average count, which, after normalization, would be 1. Non ideal bins
would have a normalized value greater or smaller than 1.
4. Subtract 1 from the normalized code count
5. Result  DNL(±0.2 LSB in this case)
6. We can reconstruct the exact converter characteristic by knowing Width of
all codes derived from measured DNL (Code=DNL+1LSB). INL is then
measured by deviation from a straight line through the end points. INL can
also be measured by doing integral of DNL.

21. 21
Figure-12 : DNL and INL Extracted from histogram DNL=±0.2 LSB, INL=
0.04 LSB

22. 22
AC Performance
An ADC is defined by its bandwidth (the range of frequencies it can measure) and
its signal to noise ratio (how accurately it can measure a signal relative to the noise
it introduces). The actual bandwidth of an ADC is characterized primarily by its
sampling rate, and to a lesser extent by how it handles errors such as aliasing. The
dynamic range of an ADC is influenced by many factors, including the resolution
(the number of output levels it can quantize a signal to), linearity and accuracy
(how well the quantization levels match the true analog signal) and jitter (small
timing errors that introduce additional noise). The key specs to review are signal-
to-noise ratio (SNR), signal-to-noise and distortion ratio (SINAD), total harmonic
distortion (THD), and spurious-free dynamic range (SFDR). SINAD is defined as
the RMS value of an input sine wave to the RMS value of the noise of the
converter (from DC to the Nyquist frequency, including harmonic [total harmonic
distortion] content). Harmonic occurs at multiples of the input frequency. SNR is
similar to SINAD, except that it does not include the harmonic content. Thus, the
SNR should always be better than SINAD. Bot SNR and SINAD are typically
measured in dB.
SINAD = [6.02(N) +1.76] (dB) ------------------------------ (3)
Where, N is number of bits.
It equation (3) is rewritten in terms of N, it would reveal how many bits of
information are obtained as a function of the RMS noise:
N=(SINAD-1.76)/6.02 ------------------------------ (4)
Equation (4) is the definition of effective number of bits, or ENOB.
SINAD is a function of the input frequency. As frequency increases toward the
Nyquist limit, SINAD decreases. Thus, the performance will be much worse near
Nyquist frequency as compared to low frequencies.

23. 23
SNR is the signal-to-noise ratio with the distortion components removed. SNR
reveals where the noise floor of the converter is. One way to improve SNR is to
oversample, which provides a processing gain. Oversampling is a method of
lowering the noise floor of the converter by sampling at a rate much higher than
the signal of interest. This spreads the noise out over a wider range in the
frequency domain, thereby effectively reducing the noise at any one frequency bin.
A 2× oversampling reduces the noise floor by 3 dB. SNR can be computed using
𝑺𝑵𝑹 = [
𝑽𝒔𝒊𝒈𝒏𝒂𝒍, 𝒓𝒎𝒔
𝑽𝒏𝒐𝒊𝒔𝒆, 𝒓𝒎𝒔
] 𝒅𝑩
Spurious-Free Dynamic Range (SFDR) is defined as the ratio of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of
the next largest spurious component, excluding DC offset. It is typically expressed
in decibels relative to the carrier (dBc). SFDR is important in certain
communication applications that require maximizing the dynamic range of the
ADC. Spur prevent the ADC from converting small input signals, because the
distortion component can be much larger than the signal of interest. This limits the
dynamic range of the ADC. A large spur in the frequency domain in the frequency
domain may not significantly affect the SNR, but will significantly affect the
SFDR.
Total Harmonic Distortion (THD) measures the distortion content of a signal,
and is specified in decibels relative to the carrier (dBc). For ADCs, THD is the
ratio of the RMS sum of the selected harmonics of the input signal to the
fundamental itself. Only harmonics within the Nyquist limit are included in the
measurement.
𝑇𝐻𝐷 = 10log[
𝑉2
2
+ 𝑉3
2
+ ⋯ + 𝑉𝑛
2
𝑉1
2 ] 𝑑𝐵
In many applications, the actual signal of interest occupies a smaller bandwidth,
BW, which is less than the Nyquist bandwidth. If digital filtering is used to filter

24. 24
out noise components outside the bandwidth BW, then a correction factor (called
process gain) must be included in the equation for the resulting increase in SNR.
𝑆𝑁𝑅 = 6.02𝑁 + 1.76𝑑𝐵 + 10𝑙𝑜𝑔10
𝑓𝑠
2. 𝐵𝑊
over the bandwidth BW. The process of sampling a signal at a rate which is greater
than twice its bandwidth is referred to as oversampling.
Figure-13 shows circuit used to calculate AC Characteristics of 3 Bit Flash ADC.
Figure-13 Test Circuit to measure AC Characteristic of 3 Bit Flash ADC

25. 25
Figure-14: FFT Plot schematic (excluding parasitic) for fin=3.891KHz, fs=500
KHz, m= 127, N=16384, tsim= 32.168 ms , SINAD= 16.162 dB,

26. 26
Figure-15: FFT Plot including parasitic fin=3.891KHz, fs=500 KHz, m= 127,
N=16384, tsim= 32.168 ms , SINAD= 9.0107 dB

27. 27
CHAPTER-
CONCLUSION
INL and DNL results shows that there is no missing code. We get SINAD= 9.0107
(including parasitic) and SINAD=16.162 (excluding parasitic). It results in
ENOB=1.21 and 2.39 respectively.Results shows that significant distortion is
present which reduces Effective Number of Bits. This is generally expected as
Flash ADC works in open loop conditions. Calibration can be done to reduce
distortion in the circuit.
FUTURE WORK
Calibration can be done to improve performance of ADC. If better results can be
obtained for three bit flash ADC, we can target for six bit flash ADC. ADC choice
depends on application and as per need. We can use pipeline ADC and flash ADC
can be employed for achieving higher resolution without compromising much on
speed.

28. 28
REFERENCE
1. Baker, R. Jacob. CMOS: circuit design, layout, and simulation. Vol. 18.
John Wiley & Sons, 2011.
2. Gray, P. "EE247 lectures." University of California at Berkeley (1996).
3. Kester, Walt. "Mt-022: Adc architectures iii: Sigma-delta adc
basics." Analog Devices, Rev. 0: 02-06.
4. Razavi, Behzad, and Bruce A. Wooley. "Design techniques for high-speed,
high-resolution comparators." Solid-State Circuits, IEEE Journal of 27.12
(1992): 1916-1926.
5. Yukawa, Akira. "A cmos 8-bit high-speed a/d converter ic." Solid-State
Circuits, IEEE Journal of 20.3 (1985): 775-779.
6. Maloberti, Franco. "Layout of analog and mixed analog-digital
circuits." Design of analog-digital VLSI circuits for telecommunications and
signal processing. Prentice-Hall, Inc., 1994.
7. Kester, Walt. "MT-001: Taking the Mystery out of the Infamous Formula,"
SNR= 6.02 N+ 1.76 dB," and Why You Should Care." REV. 0 (2005): 10-
03.
8. Mason, Martin. "The ABCs Of ADCs-Engineering Essentials-Maxim
Integrated Products-This crash course on specifying analog-to-digital
converters may tip the performance scales in your design's
favor." Electronic Design 57.19 (2009): 35.

29. 29
9. Uyttenhove, Koen, and Michiel SJ Steyaert. "A 1.8-V 6-bit 1.3-GHz flash
ADC in 0.25-μm CMOS." Solid-State Circuits, IEEE Journal of 38.7
(2003): 1115-1122.
10.Kertis, Robert A., et al. "A 20 GS/s 5-bit SiGe BiCMOS dual-Nyquist flash
ADC with sampling capability up to 35 GS/s featuring offset corrected
exclusive-or comparators." Solid-State Circuits, IEEE Journal of 44.9
(2009): 2295-2311.
11.Kundert, Ken, et al. "Design of mixed-signal systems-on-a-
chip." Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on 19.12 (2000): 1561-1571.
12.Jeon, HeungJun. "Low-power high-speed low-offset fully dynamic CMOS
latched comparator." (2010).
13.Jincheol Yoo, Kyusun Choi, Ali Tangel, “A -GSPS CMOS Flash A/D
converter for System-on-Chip Applications”, IEEE Computer society
workshop on VLSI, pp. 135-139, Apr. 2001.
14.A Abel and K Kurtz, “Fast ADC”, IEEE Trans. Nucl. Sci., vol. NS-22, pp.
446-451, Feb. 1975