To design a low power processor, low power Arithmetic and Logic Unit (ALU) is required, since ALU is one of the core components and most power hungry sections in a microprocessor that carries out the arithmetic and logic operations. Clock gating is the power saving technique used for low power design, it switches off the module which is not active as decided by selection line.
This techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Control signal gating technique provides power saving by reducing unnecessary switching activity on datapath buses, when a bus is not going to be used and it will be held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. For
designing a proposed Power Efficient ALU, both the clock gating and the control-signal gating techniques are introduced for minimizing the clock power and to reduce the unnecessary switching activity of data path. Functionality of proposed ALU is verified by using Xilinx tool and power analysis is carried out by using Xilinx X’Power analysis tool.
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...Anil Yadav
In this paper, we have presented an ALU (Arithmetic and Logic Unit) with a control-signal gating technique for reducing the switching activity on datapath buses.
The main idea behind this logic is the control-signal gating technique that will detect the bus, which is not going to be used and it will turn on only that unit which is functioning and switch-off the module which is not functioning. Control-gating circuit employs a series of AND gate on the input bus line which is controlled by a decoder. We have compared the dynamic power of proposed ALU model with conventional ALU by considering target FPGA device Virtex-6 low power with speed grade -1L.
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
Digital Implementation of Fuzzy Logic Controller for Real Time Position Contr...IOSR Journals
Fuzzy Logic Controller (FLC) systems have emerged as one of the most promising areas for
Industrial Applications. The highly growth of fuzzy logic applications led to the need of finding efficient way to
hardware implementation. Field Programmable Gate Array (FPGA) is the most important tool for hardware
implementation due to low consumption of energy, high speed of operation and large capacity of data storage.
In this paper, instead of an introduction to fuzzy logic control methodology, we have demonstrated the
implementation of a FLC through the use of the Very high speed integrated circuits Hardware Description
Language (VHDL) code. FLC is designed for position control of BLDC Motor. VHDL has been used to develop
FLC on FPGA. A Mamdani type FLC structure has been used to obtain the controller output. The controller
algorithm developed synthesized, simulated and implemented on FPGA Spartan 3E board.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...Anil Yadav
In this paper, we have presented an ALU (Arithmetic and Logic Unit) with a control-signal gating technique for reducing the switching activity on datapath buses.
The main idea behind this logic is the control-signal gating technique that will detect the bus, which is not going to be used and it will turn on only that unit which is functioning and switch-off the module which is not functioning. Control-gating circuit employs a series of AND gate on the input bus line which is controlled by a decoder. We have compared the dynamic power of proposed ALU model with conventional ALU by considering target FPGA device Virtex-6 low power with speed grade -1L.
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
Digital Implementation of Fuzzy Logic Controller for Real Time Position Contr...IOSR Journals
Fuzzy Logic Controller (FLC) systems have emerged as one of the most promising areas for
Industrial Applications. The highly growth of fuzzy logic applications led to the need of finding efficient way to
hardware implementation. Field Programmable Gate Array (FPGA) is the most important tool for hardware
implementation due to low consumption of energy, high speed of operation and large capacity of data storage.
In this paper, instead of an introduction to fuzzy logic control methodology, we have demonstrated the
implementation of a FLC through the use of the Very high speed integrated circuits Hardware Description
Language (VHDL) code. FLC is designed for position control of BLDC Motor. VHDL has been used to develop
FLC on FPGA. A Mamdani type FLC structure has been used to obtain the controller output. The controller
algorithm developed synthesized, simulated and implemented on FPGA Spartan 3E board.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
Design of Fuzzy Logic Controller for Speed Regulation of BLDC motor using MATLABijsrd.com
Brushless DC (BLDC) motors drives are one of the electrical drives that are rapidly gaining popularity, due to their high efficiency, good dynamic response and low maintenance. The design and development of a BLDC motor drive for commercial applications is presented. The aim of paper is to design a simulation model of inverter fed PMBLDC motor with Fuzzy logic controller. Fuzzy logic controller is developed using fuzzy logic tool box which is available in Matlab. FIS editor used to create .FIS file which contains the Fuzzy Logic Membership function and Rule base. And membership functions of desired output. After creating .FIS file it is implemented in the Matlab Simulink. And the BLDC motor is run satisfactorily using the Fuzzy logic controller.
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
SPEED AND TORQUE CONTROL OF AN INDUCTION MOTOR WITH ANN BASED DTCijics
Due to advantages such as fast dynamic response, simple and robust control structure, direct torque
control (DTC) is commonly used method in high performance control method for induction motors. Despite
mentioned advantages, there are some chronically disadvantages with this method like high torque and
current ripples, variable switching behaviour and control problems at low speed rates. On the other hand,
artificial neural network (ANN) based control algorithms are getting increasingly popular in recent years
due to their positive contribution to the system performance. The purpose of this paper is investigating of
the effects of ANN integrated DTC method on induction motor performance by numerical simulations. For
this purpose, two different ANN models have been designed, trained and implemented for the same DTC
model. The first ANN model was designed to select optimum inverter and the second model was designed to
use in the determination of the flux vector position. Matlab/Simulink model of the proposed ANN based
DTC method was created in order to compare with the conventional DTC and the proposed DTC methods.
The simulation studies proved that the induction motor torque ripples have been reduced remarkably with
the proposed method and this approach can be a good alternative to the conventional DTC method for
induction motor control.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Integrated fuzzylogic controller for a Brushless DC Servomotor systemEhab Al hamayel
This presentation discusses the designing and simulation of "Integrated fuzzylogic controller for a Brushless DC Servomotor system" using Matlab simulink
This slides most useful for the Engineering students and Industries peoples. Hence, they are updating the knowledge of microprocessor involved in Mechatronics system.
To impart knowledge about the elements, techniques and sensors involved in mechatronics systems which are very much essential to understand the emerging field of automation.
Bi directional speed control of dc motor and stepper motor through mat lab us...eSAT Journals
Abstract In any industry speed control of an electric drive system is very critical and crucial. Every designer aims at achieving a control methodology having high degree of precision. But industry needs are ever evolving in nature. Hence it is very much essential that along with conventional speed control mechanisms we must also have simple interactive graphical based control strategies. Several algorithms/methodologies have been developed over the years to achieve speed control of motors. In this context by encompassing the usability of Mat Lab, work has been done to control the speed of stepper motor and DC motor using microcontroller. Microcontroller is programmed to achieve bi directional speed control. The main objective of this work is to develop the graphical user interface of motor control through mat Lab guide and the interface of the same with hardware via serial communication. PIC is used as the controller. Keywords— DC, PIC, μC, AC, GUI, IC
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits.
One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper
we will present a comparative analysis of existing clock gating techniques on some synchronous digital design
like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the
existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using
tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND
logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All
experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using
XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the
hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%.
Keywords — Tri state buffer; VLSI; Xilinx; glitches; hazards;Sparten.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
Design of Fuzzy Logic Controller for Speed Regulation of BLDC motor using MATLABijsrd.com
Brushless DC (BLDC) motors drives are one of the electrical drives that are rapidly gaining popularity, due to their high efficiency, good dynamic response and low maintenance. The design and development of a BLDC motor drive for commercial applications is presented. The aim of paper is to design a simulation model of inverter fed PMBLDC motor with Fuzzy logic controller. Fuzzy logic controller is developed using fuzzy logic tool box which is available in Matlab. FIS editor used to create .FIS file which contains the Fuzzy Logic Membership function and Rule base. And membership functions of desired output. After creating .FIS file it is implemented in the Matlab Simulink. And the BLDC motor is run satisfactorily using the Fuzzy logic controller.
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
SPEED AND TORQUE CONTROL OF AN INDUCTION MOTOR WITH ANN BASED DTCijics
Due to advantages such as fast dynamic response, simple and robust control structure, direct torque
control (DTC) is commonly used method in high performance control method for induction motors. Despite
mentioned advantages, there are some chronically disadvantages with this method like high torque and
current ripples, variable switching behaviour and control problems at low speed rates. On the other hand,
artificial neural network (ANN) based control algorithms are getting increasingly popular in recent years
due to their positive contribution to the system performance. The purpose of this paper is investigating of
the effects of ANN integrated DTC method on induction motor performance by numerical simulations. For
this purpose, two different ANN models have been designed, trained and implemented for the same DTC
model. The first ANN model was designed to select optimum inverter and the second model was designed to
use in the determination of the flux vector position. Matlab/Simulink model of the proposed ANN based
DTC method was created in order to compare with the conventional DTC and the proposed DTC methods.
The simulation studies proved that the induction motor torque ripples have been reduced remarkably with
the proposed method and this approach can be a good alternative to the conventional DTC method for
induction motor control.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Integrated fuzzylogic controller for a Brushless DC Servomotor systemEhab Al hamayel
This presentation discusses the designing and simulation of "Integrated fuzzylogic controller for a Brushless DC Servomotor system" using Matlab simulink
This slides most useful for the Engineering students and Industries peoples. Hence, they are updating the knowledge of microprocessor involved in Mechatronics system.
To impart knowledge about the elements, techniques and sensors involved in mechatronics systems which are very much essential to understand the emerging field of automation.
Bi directional speed control of dc motor and stepper motor through mat lab us...eSAT Journals
Abstract In any industry speed control of an electric drive system is very critical and crucial. Every designer aims at achieving a control methodology having high degree of precision. But industry needs are ever evolving in nature. Hence it is very much essential that along with conventional speed control mechanisms we must also have simple interactive graphical based control strategies. Several algorithms/methodologies have been developed over the years to achieve speed control of motors. In this context by encompassing the usability of Mat Lab, work has been done to control the speed of stepper motor and DC motor using microcontroller. Microcontroller is programmed to achieve bi directional speed control. The main objective of this work is to develop the graphical user interface of motor control through mat Lab guide and the interface of the same with hardware via serial communication. PIC is used as the controller. Keywords— DC, PIC, μC, AC, GUI, IC
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits.
One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper
we will present a comparative analysis of existing clock gating techniques on some synchronous digital design
like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the
existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using
tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND
logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All
experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using
XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the
hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%.
Keywords — Tri state buffer; VLSI; Xilinx; glitches; hazards;Sparten.
Performance Comparison of Various Clock Gating Techniquesiosrjce
Clock signal have been a great source of power dissipation in synchronous circuits because of high
frequency and load. So , by using clock gating one can save power by reducing unnecessary switching activity
inside the gated module. Here four gating methods are discussed and their power dissipation is compared. The
most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It
unfortunately leaves the majority of the clock pulses driving the flip flops (FFs) redundant. A data driven
method stops most of those and yields higher power savings, but its implementation is complex and application
dependent. A third method called auto gated FFs (AGFF) is simple but yields relatively small power savings.
Another novel method called Look Ahead Clock Gating (LACG) is presented, which combines all the three.It
avoids the tight timing constraints of AGFF and data driven by allotting a full clock cycle for the computation of
the enabling signals and their propagation.
Implementation of T-Junction Traffic Light Control System Using Simatic S7-20...IJERA Editor
A conventional traffic light control system is designed by using devices such as timers, relays and
contactors etc. The critical timing operation is required to be carried out under the existence of heavy
traffic situations. This conventional practice leads to many problems that need additional maintenance
cost and subsequent delay for a long time. With the help of a PLC, the requirement of fast automation
and effective optimization of traffic light control system can be achieved. Use of PLC helps us to
develop this process not only for traffic signal on the roads, but also on the movement of trains and
the transfer of containers in ports in maritime works. In order to provide a solution to the above
problem, this paper introduces an execution and implementation of T-junction traffic control system
using SEIMENS S7-200 PLC. Programming in PLC is written in ladder logic with the help of STEP7
MICROWIN software
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
CPUs in general-purpose personal computers, such as desktops and laptops, dissipate significantly more power in the order of few watts because of their higher complexity and speed. ALU is a fundamental building block of CPU. It does all process related to arithmetic and logic operations. As the operations become more complex, the ALU become more complex, more expensive, takes up more space in the CPU and contributes more power dissipation within the CPU. Hence power consumption of ALU is a major issue in the designing of CPU.
Emergency power control systems is the last line of defense to avoiding facility downtime. Learn how about redundant power control automation concepts and architectures.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
3. 9
This article can be downloaded from http://www.ijeetc.com/currentissue.php
Int. J. Elec&Electr.Eng&Telecoms. 2015 Anil Kumar Yadav and Mohammed Aneesh Y, 2015
dissipated only in datapaths and clocks. So,
to reduce the power of clock and data path,
clock and control signal gating techniques are
introduces.
loaded into registers infrequently but the clock
signal continues to switch at every clock cycle
often driven a large capacitive load. So, a
significant amount of power can be saved by
identifying when the registers are inactive and
disabling the clock during these periods. This
technique has been extensively used for
dynamic power reduction in low power
applications. However, at any particular instant
only a single module may be functional, but
unnecessary clocking of the other modules
lead to a lot of power dissipation. Hence,
Clock gating technique is a power down
methodology, which involves selectively
clocking modules as and when required while
keeping other inactive modules in quiescent
mode. Thus the power consumption due to
charging and discharging of the clock at
unused gates, is avoided in this strategy.There
are three types of clock gating:
a) Latch based clock gating
b) Flip flop based clock gating
c) AND/OR gate based clock gating
Latch Based Clock Gating
Latch based clock gating techniques employs
a level-sensitive latch to the design as shown
in Figure 2, for holding the enable signal from
the active edge of the clock until the inactive
edge of the clock (Frank Emnett and Mark
Biegel, 2000). Since the latch captures the
state of the enable signal and holds it until the
generation of complete clock pulse cycle and
it is necessary for enable signal to be stable
up to the rising edge of the clock pulse.
Flip-Flop Based Clock Gating
The Flip-Flop based clock gating technique
consists of a level sensitive latch in design as
Figure 1: Power Distribution
in High-Performance CPU
A Simple Microprocessor contain register
files, an ALU and Control Circuit. ALU is the
core of microprocessors where all
computations are being performed it is one of
the most power hungrysections of its data path
andclockpower.Fordesigningapowerefficient
ALUbecomesa majorissue to reduce theclock
power and switching activity of data paths.
According to reference (Kapadia et al., 1999;
andKamaraju etal., 2010). Poweroptimization,
traditionally relegated to the synthesis and
circuits level, nowit shifted to the System Level
and Register-Transfer-Level (RTL). This is
possible due to clock gating and control signal
gating. Clock gating techniques turn off the
inactive units of the design and control signal
gating stop the propagation of switchingactivity
of data path by detecting the bus which is not
active by the help of selection line.
Clock Gating Techniques
Clock power constitutes a significant portion
of dynamic power. In many designs, data are
4. 10
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OR gate at the signal path to stop the
propagation of signal, when it needs to be
masked.Another techniques is to use a latch
or flip-flop to block the propagation of the
signal. Sometimes, a transmission gate or a
tristate buffer can be used in place of a latch if
charge leakage is not concern. All signal-
gating method requires control signals to stop
the propagation of switching activities, that's
why it'sname given control-signal gating, as
shown in Figure 4.
Figure 2: Latch Based Clock Gating
Figure 3: Flip-Flop Based Clock Gating
Figure 4: Control-Signal Gating
shown in Figure 3, to hold the enable signal
from the active edge to the inactive edge of
the clock.
AND/OR Gate Based Clock Gating
InAND/OR gate based clock gating technique
uses the AND/OR gate for controlling of the
clock signal. InAND gate clock gating clock is
active on the rising edge of the input clock,
whereas in OR gate clock gating signal is
active on the falling edge of the clock.
Control-Signal Gating Techniques
The control-signal technique employs the
advantage of a fine granularity analysis to
reduce the switching activity in the datapaths
buses. The method is based on the
Observability Don’t Care concept (ODC) to
detect when a bus is not used and to stop the
propagation of the switching activity through
the module(s) driving the bus. There are many
different ways to implement control-signal
gating. The simplest method is to put anAND/
CONVENTIONAL16-BIT ALU
WITHOUT GATING
Functionalof Conventional16-Bit ALU
The basic blocks of a computer are Central
Processing Unit (CPU), memory unit, and
input/output unit. CPU of the computer is
basically the same as the brain of a human
being. It contains all the registers, control unit
and theArithmetic Logic Unit (ALU).Arithmetic
and Logic Unit (ALU) is considered as one of
the common and the most crucial components
of microprocessor. UsuallyALU’s consists of
a number of functional blocks/units for different
arithmetical, logical and shifting operation
which are realized using combinational circuits.
Each of the functional blocks/unit performs a
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specific arithmetical, logical or shifting
operation. Therefore, the ALU is one of the
hottest spots in the datapaths.ALU takes 16-
bit operands as inputs, process the operand
data and gives 16-bit output data. Following
operation is performed by conventionalALU,
described in Table 1.
0000 Add 1000 AND
0001 Subtract 1001 OR
0010 Increment 1010 NOT
0011 Decrement 1011 EXOR
0100 Multiply 1100 Shift left
0101 Division 1101 Shift right
0110 Clear 1110 Rotate left
0111 Set 1111 Rotate right
Table 1: Function of ALU
Select
Operation
Arithmetic
Operation
Select
Operation
Logic
Operation
PROPOSED ALU MODEL
WITH CLOCK AND
CONTROL-SIGNAL GATING
Architecture of Proposed ALU
Instead of designing ALU as a single
module, it is divided into sixteen functional
blocks, which is select by Clock gating
technique, but there is problem that when one
module is functioning, all other 15 input bit
lines will be always in active mode, causes
more switching power dissipation. To
remove this problem, we introduces control
signal gating techniques, which will activate
only that line which is required for operation
and deactivate other functional line similar
to clock gating techniques. Proposed
Architecture of is shown in Figure 8, which
consist of clock gating and control-signal
gating circuit feeded to ALU module.
Clock Gating Circuit: It is combination of 4 x
16 decoder and 16 AND logic gate, in which
clock signal isANDed with output of decoder,
which will select one of sixteen AND gate as
decided by opcode. Hence, clock gating circuit
acts as a clock selector, which can select one
of the sixteen block of any architecture which
requires clock.
Control Signal Gating Circuit: It is a
combination of two 1 x 16 Demux, which is
controlled by a control-signal, (as shown in
Figure 8). We are applying input signal to this
block and it will give a pair of sixteen
combination of output line, which will be used
to feed the ALU block as a input pair line.
Controlled line willselect only one pairof output
line, i.e., one time only one output line will
activate and other fifteen will be off. Hence, in
this way, it saving the switching power
consumption on datapath buses.
The Top level schematic view and Timing
waveform of Conventional ALU is shown in
Figures 5 and 6 respectively.
Figure 5: Top Level Schematic View
of Conventional ALU
Figure 6: Timing Waveform
of Conventional ALU
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Clock distribution of proposed ALU is
shown in Figure 7.
Function of Proposed ALU
Function of proposed ALU can be explained
as follows: There is two inputs line in
proposed ALU architecture: one is clock
signal (Clock) and another is selection line
(SEL). SEL line has feeded to Control signal
gating circuit, clock-gating circuit and also
to out DEMUX. It acts as a opcode signal
for Decoder in Clock gating circuit, which
will selects one of the sixteen AND gates
of clock-feeded AND logic in clock-gating
circuit. SEL is also feeded to control-signal
gating circuit as a controlling signal. Hence,
in this way, SEL line is act as a control
signal for ALU operation.
For example, when selection line is “0000”,
then opcode will be “0000”, then it will selects
Figure 8: Proposed Architecrue of ALU with Clock and Control-Signal Gating
Figure 7: Clock Distribution in Proposed
ALU Model
AND 1 gate, which in turn sends clock signal
to the first functional block of ALU, while for
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remaining fifteen units clock signals are not
allowed, at a time.
Control-signal gating circuit activate only
first input lines of first block and deactivate
other fifteen inputs line and then, out mux will
select output of first functional block because
of selection line input as feeded. Hence, it's
saving about 93.7 (15/16)% switching activity
power of its input data path and about 93.7
(15/16)% clock power.
The timing waveform and top level
schematic of proposed ALU is shown in
Figure 9 and Figure 10 respectively.
Figure 9: Timing Waveform of Proposed
Model
Figure 10: Top Level RTL View
of Proposed Model
RESULTS
Power Comparison
The dynamic and total Power of conventional
and proposed Model is calculated by Xilinx
X’Power Analyzer tool considering target
FPGA Device Virtex-6 Low power with speed
grade –1 L. Power of both model is given in
Table 2. and dynamic power comparison is
shown in Figure 11.
Total power 1176 mW 1171 mW
Dynamic power 77 mW 72 mW
Quiescent power 1099 mW 1099 mW
Table 2: Power Comparison of Both Model
Parameter
Conventional
Model
Proposed
Model
Figure 11: Dynamic Power Comparison
From the above synthesis result and table,
it is observed that the Dynamic power of
proposed model is reduced in comparison
to conventional model. Hence, clock and
control-signal gating can be implemented as
a power efficient techniques to reduce the
dynamic power of device.
Device Utilization Summary
Device utilization summary of both the model
(conventional as well as Proposed) is shown
Figure 12 and Figure 13 respectively.
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Int. J. Elec&Electr.Eng&Telecoms. 2015 Anil Kumar Yadav and Mohammed Aneesh Y, 2015
is power efficient technique to optimize the
power of clock and datapath buses.
In this project work, there are still some
improvements could be done in the future for
improving the performance of ALU by
introducing Low power adder and multiplier
unit. We can also improve in Clock and Control
signal gating techniques by replacing it with
appropriate circuit model. This techniques can
also be implemented at architecture level, by
introducing clock gating and other low power
design techniques, we can improve the
dynamic power performance of
Microprocessor and other power hungry
devices.
REFERENCES
1. Bishwajeet Pandey and Manisha
Pattanaik (2013), “Clock Gating Aware
Low Power ALU Design and
Implementation on FPGA”, International
Journal of Future Computer and
Communication, Vol. 2, No. 5.
2. Christian Piguet (2005), “Low-Power
CMOS Circuits: Technology, Logic
Design and CAD Tools”, CRC Press.
3. Frank Emnett and Mark Biegel (2000),
“Power Reduction Through RTL Clock
Gating”, SNUG, San Jose.
4. Hamid Mahmoodi, Tirumalashetty V,
Matthew Cooke and Kaushik Roy (2009),
“Ultra Low-Power Clocking Scheme
Using Energy Recovery and Clock
Gating”, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems,
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5. Ireneusz Brzozowski and Andrzej Kos
(1999), “Minimization of Power
Figure 12: Device Utilization Summary
of Conventional Model
Figure 13: Device Utilization Summary
of Proposed Model
CONCLUSION
There are several approaches to reduce the
dynamic power. In this project work, ALU
model with clock gating and control signal
gating technique is designed using Verilog
HDL, simulated and synthesized using Xilinx
ISE 13.2 considering Virtex Low power with a
speed grade–1 L, to optimize the power and
it is found thatALU with both clock gating and
control-signal techniques consumes less
power than conventional ALU. Hence, it is
concluded that clock and control-signal gating
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Int. J. Elec&Electr.Eng&Telecoms. 2015 Anil Kumar Yadav and Mohammed Aneesh Y, 2015
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