This document describes the Illinois Scan Architecture, a technique for reducing test costs for chips with scan designs. It works by dividing the main scan chain into multiple parallel internal chains, with a single scan input pin. This allows test vectors to be broadcast to all chains simultaneously, reducing test time and data volume by the number of chains with little impact on fault coverage. The document provides experimental data showing reductions in test vectors, cycles, and data volume for several ISCAS circuits using Illinois Scan. It also discusses techniques for further optimizing the technique, such as grouping chains intelligently to minimize the number of scan input pins needed.

1. Illinois Scan Architecture
Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
jhpatel@illinois.edu

2. 2
Cost of a Chip
 300mm wafer will give 700 ~1cm2 chips
 Material Costs (wafer, copper etc) ~5%
 Fab amortization cost ($3B/fab) plus
Fab operational cost ~25%
 Personnel cost ~20%
 Package Cost ~10%
 Testing Cost ~40% !!!
Semiconductor Wafer
Manufacturing test is done
at wafer level without cutting
out the chips.

3. 3
Cost of Testing Semiconductor Chips
 Three main variable components
 Test Application Time
 When amortizing the cost of a tester over all chips,
higher test time results in to higher actual cost
 Rule of thumb: 1 second per chip!
 Test Data Volume
 Low and medium cost testers have limited storage
 Tester Pins
 Cost of a tester is directly proportional to the number
of pins it supports

4. 4
Example: An IBM chip
 7million gates (logic only, RAM not included)
 250k Flip-Flops
 Full Scan design, all FFs connected as shift
register
 7000 Test Vectors
 Test Application Time: 7000x250k = 1.75G cycles
 at 100MHz scan speed it takes 17.5 Seconds!
 at 500MHz scan speed it takes 3.5 Seconds
 Tester memory required: 7000x250k = 1.75G bits
250,000 ffs
Scan
in
Scan
out

5. 5
Parallel Scan
Scan-in
1000 Parallel Scan Chains by 250 FFs
Scan Channels on most Testers range from 10 to 200
Scan-out
Reduces Test Vector Load time by a factor of 1000!
1000
scan-in pins!
1000
scan-out pins!

6. 6
Parallel Scan Output Compaction
Scan-in
100 Parallel Scan Chains by 2500 FFs output
compactor
A Combinational Compactor is a tree of XOR gates
A Sequential Compactor is a Linear Feedback Shift Register with
multiple parallel inputs XORed. Also called a Multiple Input
Signature Analyzer (MISR)

7. 7
Parallel Scan - Summary
 Scan loading time can be reduced by dividing the
single scan chain in to parallel scan chains
 Some Observations
 Output Compaction is well established
 Number of scan chains is limited by the availability
of pins on a chip and tester scan channels
 Additional “pins” on an embedded core require
more routing in the SOC
Parallel Scan has no impact on test data volume

8. 8
Test Vector Compaction
 For example, all 40 ISCAS 85 and
ISCAS89 (full scan) circuits, sizes
of the test sets generated by
MinTest (Hamzaoglu and Patel, ICCAD
1998, pp. 283-289) meets Lower
bounds for 31 out of 40 ISCAS
circuits.
 This shows that Compaction
has already reached theoretical
lower bounds in many
instances
 Need solutions beyond vector
compaction
Test Vectors
Circuit
Lower
Bound
Min
Test
C432 27 27
C5315 37 37
C7552 65 73
S1196 113 113
S1423 20 20
S5378 97 97
S38714 62 68

9. 9
BIST: STUMPS Architecture
P. H. Bardell and W. H. McAnney, “Self-Testing of Multichip Logic Modules,”
Proc. Of Int. Test Conf., pp. 200-204, Nov. 1982. (used by IBM for multi-chip-modules)
L
F
S
R
Scan Chain
Scan Chain
Scan Chain
Scan Chain
Phase
Shifter
M
I
S
R
Circuit Under Test
This has the same limitations as any other BIST based scheme
Linear
Feedback
Shift
Register
Multiple
Input
Signature
Register

10. 10
Limitations of Logic BIST
 BIST is excellent for Data Volume Reduction, But
 Lower Fault Coverage. Test Point insertion and/or
additional logic in test generator is required to
cover Random Resistant Faults
 Design Modification needed to permit any arbitrary
test pattern
 Tri-State logic must be fully decoded
 No floating bus is permitted, since unknown values
can corrupt the signature
 Switching activities of various modules, and hence
the power, cannot be easily controlled
 Will almost always increase the tester time!
 Failure Diagnosis becomes extremely difficult

11. 11
Proposed New Method
 Illinois Scan Architecture
 Applicable to full-scan embedded cores and full-
scan stand-alone chips
 Addresses all issues raised earlier –
Low test application time, low pin overhead, and
low test data volume
 Does not have any of the limitations of the BIST
 No test point insertions and No design
modifications!
 Undesirable test vectors can be filtered, e.g.,
Vectors that produce Tri-State Conflicts, Unknown
value generation, or High switching activity

12. 12
Illinois Scan Architecture
Take a Serial Scan
1. Divide it up into several chains
keeping the same Scan-in pin
2. Add a MISR to compact the outputs
Scan
in
Scan
out
MISR
Scan
in
Scan
out

13. 13
Illinois Scan
Internal Scan Chains
Scan-in
pin
Output
Compactor

14. 14
Untestable Faults in Illinois Scan
 In the figure shown on left,
all three scan chains will
have identical test vectors
 Therefore, only applicable
test vectors are 000 and
111 for the AND gate
 Test vectors 110, 011 and
101 cannot be applied due
to Broadcast constraint
 This makes three faults on
the AND gate Untestable
scan in
1
1
1
0
0
0
In practice, how serious is this problem?
How many faults become untestable?

15. 15
Additional Untestable Faults
 Illinois Scan puts constraints
on inputs
 Cannot generate tests for
some of the faults that
are testable
 The number of such
“Additional Untestable
Faults” is surprisingly
small
 Experimental Data for
Scan Chain divided into 16
chains (arbitrary partition),
with a single scan input.
0
200
400
600
800
1000
1200
ILS-13207
ILS-15850
ILS-35932
ILS-38417
ILS-38584
Untestable
Faults

16. 16
Two Test Modes of Illinois Scan
Scan Out
Scan Chain 1
Scan Chain 2
Scan Chain n
Scan In
1. Broadcast Test Mode
1. Reduces Scan Time by a factor of n
2. Reduces Scan Data by a factor of n
But may require many more vectors
and may reduce fault-coverage!
•
•
•
M
I
S
R
Scan Chain 1
Scan Chain 2
Scan Chain n
2. Serial Test Mode
Mode 2 for covering the loss of
fault-coverage in the Broadcast Mode
Generates “top-off vectors”.
Note: Most industrial circuits do
not use Mode 2.
•
•
•
Scan In
Scan Out
M
I
S
R

17. 17
Number of Test Vectors
0
50
100
150
200
250
300
350
400
fs13207
ILS-13207
fs15850
ILS-15850
fs35932
ILS-35932
fs38417
ILS-38417
fs38584
ILS-38584
Circuit
Vectors
scan vectors
broadcast vectors
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16

18. 18
Number of Test Cycles
0
25,000
50,000
75,000
100,000
125,000
150,000
175,000
200,000 fs13207
ILS-13207
fs15850
ILS-15850
fs35932
ILS-35932
fs38417
ILS-38417
fs38584
ILS-38584
C
i
r
cui
t
C
ycl
e
s
scan cycles
broadcast cycles
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16

19. 19
Illinois Scan Data Volume
0
50,000
100,000
150,000
200,000
250,000
300,000
350,000
400,000
450,000
fs13207
ILS-arb
fs15850
ILS-arb
fs35932
ILS-arb
fs38417
ILS-arb
fs38584
ILS-arb
Circuit
Data
Bits
Scan Test Data
Broadcast Test Data
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16

20. 20
Illinois Scan
internal scan chains
scan-in
pin
output
compactor

21. 21
Illinois Scan with multiple pins
internal scan chains
external
scan-in
pins
output
compactor

22. 22
Case Study at Texas Instruments
Illinois
Scan
Version
Broadcast
Vectors
Broadcast
Fault
Coverage
Additional
Untestable
Faults
Serial
Scan
Vectors
needed
Serial
Scan
Fault
Coverage
Broadcast
Vectors
needed
Data
Volume
Reduction
Factor
DIV16 15,000 94.08% 733 53 70% 9700 1.4
DIV24 14,000 94.09% 692 38 67% 9500 2
DIV32 12,000 93.87% 1565 59 73% 8000 3
Original Circuit : 150K logic gates, 9300 scan flip-flops
910 Scan Vectors, 94.25% stuck-at fault coverage
Similar reduction was also found in Transition Fault Data
Frank Hsu, Ken Butler and Janak Patel, “A Case Study on the Implementation of the
Illinois Scan Architecture,” Int. Test Conf. Oct. 2001

23. 23
IBM Data using Illinois Scan (OPMISR+)
Design
Gate
Count
Scan
flip-flops
Test Time
Reduction
Test Volume
Reduction
Chip1 1.7M 230k 130x 200x
Chip2 2.1M 31k 38x 54x
Chip3* 715k 41k 7x 21x
Chip4* 1.2M 65k 8x 12x
“….scan fan-out, which is sometimes informally referred to as Illinois Scan [ix].
In the Cadence ATPG tools we refer to this as OPMISR+.”
Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition,
Technology Application Note, December 2003
* These chips already had their scan divided by customer

24. 24
Intel Data on Illinois Scan
From a Paper by D. Wu et. al. of Intel, published in 2003 Int.
Test Conf.
“The first test chip has 81 scan-in and 81 scan-out channels, we
use Illinois Scan with 4 scan-in and 81 scan-out. The results are
quite surprising: both methods got the same test coverage.”
“We have implemented Illinois scan into one of the
microprocessors, but the silicon results will not be ready for the
timing of this year’s ITC.”

25. 25
More Data on Illinois Scan
7M Gates, 250k flip-flops, 7000 test vectors
Source: V. Chickermane, B. Fautz and B. Keller,
Channel-Masking Synthesis for Efficient On-Chip Test Compression, Int. Test Conf., 2004.
Illinois
Scan

26. 26
Illinois Scan in CAD Tools
 Cadence (formerly IBM)
 Illinois Scan on their patented “OPMISR” is called
OPMISR+
 Syntest
 Illinois Scan is called “Virtual Scan”
 Synopsis
 ATPG Tools understand and support Illinois Scan
 Mentor Graphics
 No Illinois Scan!
 Proprietary tool called TestCompress

27. 27
Illinois Scan with multiple pins
 Large Industrial Circuits have used Illinois Scan
with multiple pins
 IBM ASIC-4 chip (Design and Test, Sept. 2002, pp. 65-72)
 1.14 million gates, 46 pins, 269 internal chains
 Intel chips (Int. Test Conf., Sept. 2003, pp. 1229-1238)
 ASIC-1, 4 pins, 81 internal chains
 ASIC-2, 4 pins, 96 internal chains
 Next generation microprocessor (no data given)
 All of the above scan-chain groupings are ad-hoc!
 Can we do better with intelligent grouping?

28. 28
Optimal Grouping of Chains
scan chains
scan-in
pins
Objective:
Minimize number of Scan-In Pins without loss in fault coverage.

29. 29
Compatibility among Chains
 Compatibility between two scan cells
 Two inputs (scan cells) are compatible if and only if
no fault becomes untestable as a result of tying the
two cells to a single input (Chen&Gupta, ITC 1995)
 Compatibility between two scan chains
 Two chains are compatible if and only if every pair
of scan-cells that receive the same broadcast
value are compatible (Hamzaoglu&Patel, FTCS 1999)
 Determination of all pairwise compatibilities is
computationally very expensive
 Resort to an inexpensive algorithm which gives a
subset of all compatible pairs

30. 30
Incompatibilities from a Test Set
A Partially Specified Test Vector, 20-bits long folded on to 5 chains
Vector 1
001x 0xx1 x01x 0011 xx11 0 0 1 x a
0 x x 1 b
x 0 1 x c
0 0 1 1 d
x x 1 1 e
0 0 1 x a
0 x x 1 b
x 1 1 x c
0 0 1 1 d
x x 1 1 e
Vector 2
001x 0xx1 x11x 0011 xx11
Chains a and c are incompatible,
so are chains c and d
No conflicting values found
Chain

31. 31
Example of Chain Grouping
A B C
D E F
G H
Given Incompatible Pairs:
AB, AD, AG, BD, BE, BF, CE, CF, EF, EG, EH, FH
Construct a Graph with Nodes=Chains and Edges=Incompatibility
Perform Graph Coloring Algorithm
A
B
C
D
E
F
G
H
Conflict-free Chain Grouping

32. 32
Dual-mode Illinois Scan
A
B
C
D
E
F
G
H
Single Pin Broadcast Mode
A
B
C
D
E
F
G
H
Group Mode

33. 33
Dual Mode for Pin Reduction
Circuit
no. of
Chains
no. of
Pins
Reduction
Factor
s13207.1
64 8 8.0
107 9 11.8
s15850.1
54 7 7.7
89 11 8.0
s38417
52 5 10.4
82 7 11.7
s38584.1
90 7 12.8
119 8 14.8

34. 34
Illinois Scan: Summary
 A simple DFT technique, ideal for reducing test
costs for large chips
 Significant reduction in test application time, test
data and test pins without loss in fault coverage
 Even a “dumb” partition is very effective!
 For large chips, 400 factor reduction is likely!
“Things should be made as simple as possible,
but not any simpler” Albert Einstein

35. 35
More information on Illinois Scan
1. I. Hamzaoglu and J.H. Patel, “Reducing test application time for full-scan
embedded cores,” Proc. 29th Int. Symp. On Fault-Tolerant Computing
(FTCS-29), pp.260-267, June 1999
2. F. Hsu, K. Butler and J.H. Patel, “A case study on the implementation of
Illinois Scan Architecture,” Proc. Int. Test Conf. pp. 538-547, October 2001
3. A.R. Pandey and J.H. Patel, “An incremental algorithm for test generation
in Illinois Scan Architecture based designs,” Proc. Of Design Automation and
Test in Europe (DATE), pp. 368-375, March 2002.
4. A.R. Pandey and J.H. Patel, “Reconfiguration techniques for reducing test
time and test data volume in Illinois Scan Architecture based designs,” IEEE
VLSI Test Symp. (VTS), pp. 9-15, April 2002.
5. M.A. Shah and J.H. Patel, “Enhancement of the Illinois Scan Architecture
for Use with Multiple Scan Inputs,” IEEE Computer Society Annual
Symposium on VLSI, pp. 167-172, Feb. 2004.