Download to read offline
More Related Content
Similar to Using VisualSim Architect for Semiconductor System Analysis
Using VisualSim Architect for Semiconductor System Analysis
- 1. EARLY ARCHITECTING EXPLORATIONUSING SYSTEM-LEVEL SIMULATION Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 2. About Mirabilis Design Foundedin 2003 and based in Sunnyvale, CA, USA. Development and support centers in US, India, China, Korea and Czech Republic Focused on system architecture exploration of electronics, semiconductors and software 40+ customers worldwide in Semiconductors, Aerospace, Computing and Automotive VisualSim- Modeling and simulation software Largest source of system modeling IP with embedded timing and power 100’s of man years experience in system design and exploration of digital electronics Select the “Right” configuration to match customer request
- 3. Basic Definitions Architecture Exploration ◦Optimize system specification to match requirements ◦ Specification: Processor speed, topology and arbitration ◦ Requirements: Timing, energy, cost, weight and efficiency Performance Analysis ◦ Buffer size, utilization, throughput and response time Power Measurement ◦ Peak and average power, energy and power/task Functional Correctness ◦ Arbitration, software task scheduling and task graph Making Better Quality Products
- 4. Types of Exploration Hardwaresystem sizing to meet the software processing, IO rates and latency needs Comparison of different technologies and protocols Enhancement to existing standards Development of custom pipeline Experiment cache-memory hierarchy Design for minimal power to meet the requirements Failure analysis and support for future capacity requirements Early certification/customer demonstration model
- 5. Application of VisualSim Monte-Carlosimulation with random samples, parameters, connectivity, traffic and use-cases Models constructed with library of pre-defined parameterized components ◦ Resource, custom development and HW/SW/NW Graphical and hierarchical construction, debugging and analysis of model Batch-mode simulation for large-scale analysis and experimentation Interfaces to languages, simulators and spreadsheets 5 Performance Analysis Power Exploration HW-SW Partitioning Failure Analysis Software Network Hardware Validate and optimize your design quickly and accurately
- 6. Largest Systems-Level IP Comprehensiveimplementation-accurate Library Traffic • Distribution • Sequence • Trace file • Instruction profile Reports • Timing deadline • Throughput • Utilization • Ave/peak power • Statistics Support • Listeners • Debuggers • Tracers • Assertions Power • State power table • Power management • Energy harvesters • Battery • RegEx operators ARM SoC • AHB/ APB/ AXI • Corelink • CoreConnect ARM SoC • Network-on-Chip • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge Board-Level • PCI/PCI-X/PCIe • Rapid IO • CAN-FD • AFDX • TTEthernet • OpenVPX • VME • SPI 3.0 • 1553B • FlexRay Processors • GPU, DSP, mP and mC • RISC-V • Nvidia- Drive-PX • PowerPC • X86- Intel and AMD • DSP- TI and ADI • MIPS, Tensilica, SH ARM • M-, R-, 7TDMI • A8, A53, A72, A76 RTL-like • Clock, Wire-Delay • Registers, Latches • Flip-flop • ALU and FSM • Mux, DeMux • Lookup table RTOS • Template • ARINC 653 • AUTOSAR Stochastic • FIFO/LIFO Queue • Time Queue • Quantity Queue • System Resource • Schedulers • Cyber Security Custom Creator • Script language • 600 RegEx methods • Task graph creator • Tracer • C/C++/Java/Python Storage • Flash & NVMe • Storage Array • Disk and SATA • Fibre Channel • FireWire Networking • Ethernet & GiE • Audio-Video Bridging • TSN & IEEE802.1Q • 802.11 and Bluetooth • 5G • Spacewire FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic template • Interface traffic generator Memory • Memory Controller • DDR DRAM 2,3,4 • LPDDR 2, 3, 4 • HBM, HMC • SDR, QDR, RDRAM
- 7. Concurrent Software Executionand Multiple IO makes System Sizing Challenging Complex behavior - input stream - data dependent behavior Contention - limited resources - scheduling/arbitration Interference of multiple applications - limited resources - scheduling/arbitration - anomalies I/O DSP CPU1 CPU2 task1 task2 task3 task4 Scheduling software tasks using limited resources
- 8. Narrowing the Rangeof Expected System Operation System with faster Bus is slower in places Unpredictable System Response
- 9. Throughput Application Latency Power Performance Requirements Power Service Latency Reliability Software TaskScheduling determines System Traffic Deadline Requirements for Applications + • Extreme system unpredictability is a fundamental characteristic of advance automotive systems • Sensor/Data/Video/Voice data arrival process difficult to predict • Real-time tasks must be assured of meeting deadlines in realistic scenarios Challenges must be studied globally, ideally in the context of power, performance, and reliability
- 10. Applications of ArchitectureExploration Systems Semiconductor Network and Constellation Stochastic Behavior model Mixed cycle-accurate Software Task Scheduling Timing-Accurate Failure Analysis Verification link Architecture Exploration includes Performance, Power and Functionality
- 11. Modeling Devices Traffic generators ◦I/O ◦ Processes or requests to slave devices and memories Processor ◦ Emulate the variation of activity to memory and devices based on a specific pipeline and cache Custom implementation to represent accelerators ◦ Functional analysis Trace-driven ◦ Use output from an existing system ◦ Using Mirabilis-provided scripts to generate traces from QEMU Integrate with Code-based models ◦ Using existing generators
- 12. Buses, Switches andSlaves Buses ◦ Use off-the-shelf technology such as AHB, AXI, Switch, bridges and PCIe ◦ Develop custom buses using Script, Resources and other basic blocks Memory ◦ Stochastic or cycle-accurate ◦ Address-based ◦ Link to multi-level cache Custom devices ◦ Use delay and Resource blocks
- 13.
- 14. Behavior to ArchitectureMapping ARM-based Architecture Model Behavior Flow Spreadsheet
- 15.
- 16.
- 17. Concept of VisualSimPower Technology Model input is list of states, associated power and power management Power consumption over time Based on system activity and state change Multiple state change at any instance with variable duration Power management logic to change state Supports network, interface, hardware and software Power impact entities ◦ Generation- wind, solar, motor, steady, custom ◦ Storage- types of batteries ◦ Consumption- rates, devices and clocks ◦ Management- time and custom Power is an integral part of Architecture Exploration Block Power Mode Diagram Function 1 Function 2 Function N . . . Functional Portion Timing 1 Timing 2 Timing N . . . Timing and Resource Portion Block Functional and Timing Diagram
- 18. Accurate Activity-based PowerAnalysis Divergence of analytical methods can lead to incorrect expectations
- 19. Performance and PowerStatistics
- 20. VisualSim Design Flow Early architecture analysis Detailed design specification Debugging during development Testand Verification In-field analysis Understanding the requirements and getting early feedback Size, Allocate, Arbitration, IP selection and topology design Compare results between development and architecture model Provide scenarios and test benches for verification Input traffic traces to recreate the problem End-to-end Design Flow Impact
- 21. Using Code-based DesignMethodology Project Schedule Model Creation (6) Implementation (18) Analysis (1.5) Communication and Refinement (6) Implementation (15) Using Model-Based Design Methodology Note: All times in months Communication and Refinement (4) Analysis (2.5) Model Creation (1) Engineering Benefits Average gain for 24 month project is 25%-30% Highest Quality Product Accelerate Model development Average increase in revenue per project = $??M
- 22. WEBINAR: MAKING EARLYARCHITECTURE DECISIONS USING SYSTEM-LEVEL SIMULATION Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com