This document discusses coding style guidelines for logic synthesis. It begins with basic concepts of logic synthesis such as converting a high-level design to a gate-level representation using a standard cell library. It then discusses synthesizable Verilog constructs and coding techniques to improve synthesis like using non-blocking assignments in sequential logic blocks. The document also provides guidelines for coding constructs like if-else statements, case statements, always blocks and loops to make the design easily synthesizable. Memory synthesis approaches and techniques for designing clocks and resets are also covered.

1. Coding Style for Good
Synthesis
VinChip Systems

2. Agenda
 Basic Concepts of Logic Synthesis
 Synthesizable Verilog constructs
 Coding for Synthesis
 Conclusion

3. Basic Concepts of Logic Synthesis
 Converting a high-level description of design into an optimized gate-level representation.
 It uses Standard Cell Library
 Basic logic elements
 and
 or
 inverter (not),
 Nand, nor …
 Macro Cells like
 adder, multiplexers,
 memory, and special flip-flops.

4. Logic Synthesis
Synthesis = Translation + Optimization +Mapping

5. Limitation on Manual Design
 Error-Prone:
 For Large Designs, We can not determine the missed gates
 Hard to Verify:
 Designer would never sure about the conversion until gate level circuit implemented
and tested
 Time-Consuming:
 Time Consuming process to convert High level design into gate level design
 Hard to reuse:
 design reuse was not possible
 Impossible to optimize globally :
 Not Possible in global optimization – Each designed might designed in different
method.

6. Logic Synthesis
 There are two parts
 Translation
 Performs architectural optimizations and then creates an internal representation of the
design.
 Usually this is automatically done while design is imported to the synthesis tool.
 Optimization
 The resulting netlist to fit constraints on speed (timing constraint) and area (area
constraint)
 Most critical part of the process
 Logic optimization + Gate optimization

7. Synthesis Flow
RTL Source :
Logic Implemented in RTL
No Timing Information
HDL – Verilog or VHDL
Constraints
Timing Specification
Maximum Fan-Out
Maximum Capacitance
Port delays ..
Technology Library
Target Library – Target components
Link Library – Resolve references
Synthetic Library –Adders ..
GTECH Library – Tech Independent

8. Coding Guidelines for Synthesis
 Goals of coding guidelines
 Testability
 Performance
 Simplification of static timing analysis
 Matching gate-level behavior with that of the original RTL codes

9. Synthesizable Verilog constructs
 All the Verilog constructs are not synthesizable
 Only a subset of Verilog constructs can be synthesized

10. HDL Compiler Unsupported
 delay
 initial
 Repeat , wait
 fork … join
 event
 Assign, deassign – reg data type
 Force - release
 time
 triand, trior, tri1, tri0, trireg
 nmos, pmos, cmos, rnmos,
 rpmos, rcmos
 pullup, pulldown
 rtran, tranif0, tranif1, rtranif0,
 case identity and not identity
operators

11. Synthesizable Verilog Constructs
 Ports - Input , output , inouts
 Parameters - parameter
 Module definitions
 Signals and Variables
 Instantiations .
 Procedural block ,
 Data flow

12. Language Structure Translations
 Synthesizable operators
 Synthesizable constructs
 assignment statement
 if .. else statement
 case statement
 loop structures
 always statement
 memory synthesis approaches

13. Blocking and Nonblocking Assignments
 Two types of assignments
 Blocking assignments execute in sequential order.
 Nonblocking assignments execute Concurrently.
 Always use non blocking assignments in Sequential blocks
 Otherwise, the simulation behavior of the RTL and gate-level designs may
differ.
 Specifically, blocking assignments can lead to race conditions and
unpredictable behavior in simulations.

14. Blocking and Nonblocking Assignments
 Use non-blocking assignments to model sequential logic
 Use blocking assignments to model combinational logic
 Do not mix blocking and non-blocking assignments in the same always block.
 Do not make assignments to the same variable from more than one always block.

15. if- else statements
Synthesizing if-else Statements
For combinational logic
Completely specified?
For sequential logic
Completely specified?
always @(enable or data)
if (enable) y = data //infer a latch
always @(posedge clk)
if (enable) y <= data;
else y <= y; // a redundant expression

16. Synthesizing case Statements
 A case statement
 Infers a multiplexer
 Completely specified?

17. Latch Inference - Incomplete case Statements
 // Creating a latch
module latch_infer_case(select, data, y);
input select;
output y;
reg y;
always @(select or data)
case (select)
2'b00: y = data[select];
2'b01: y = data[select];
2'b10: y = data[select];
// default: y = 2'b11;
endcase
 No Default Statement – Infers a latch
 // Correct code
module latch_infer_case(select, data, y);
input select;
output y;
reg y;
always @(select or data)
case (select)
2'b00: y = data[select];
2'b01: y = data[select];
2'b10: y = data[select];
default: y = 2'b11;
endcase

18. Mixed Use of posedge/level Signals
 // the mixed usage of posedge/negedge
signal
//The result cannot be synthesized
module DFF (clk, reset, d, q);
…
// the body of DFF
always @(posedge clk or reset)
begin
if (reset) q <= 1'b0;
else q <= d;
end
 // the mixed usage of posedge/negedge
signal
//The result can be synthesized
module DFF (clk, reset, d, q);
…
// the body of DFF
always @(posedge clk or negedge reset)
begin
if (reset) q <= 1'b0;
else q <= d;
end

19. Sensitivity List
 For combinational blocks
 The sensitivity list must include every signal that is read by the process.
 Signals that appear on the right side of an assign statement
 Signals that appear in a conditional expression

20. Sensitivity List
 For sequential blocks
 The sensitive list must include the clock signal.
 If an asynchronous reset signal is used, include reset in the sensitivity list.
 Use only necessary signals in the sensitivity lists
 Unnecessary signals in the sensitivity list slow down simulation

21. for Loop
 Provide a shorter way to express a series of statements.
 Loop index variables must be integer type.
 Step, start & end value must be constant.
 In synthesis, for loops are “unrolled”, and then synthesized.

22. Memory Synthesis Approaches
 A flip-flop
 10 to 20 times the area of a 6-transistor static RAM cell
 Inefficient in terms of area
 Register files in datapaths
 use a synthesis directive
 hand instantiation

23. Memory Synthesis Approaches
 RAM standard components
 supplied by an ASIC vendor
 depend on the technology
 RAM compilers
 The most area-efficient approach

24. Guidelines for Clocks
 Using single global clock
 Avoiding using gated clocks
 Avoiding mixed use of both positive and negative edge-triggered flip-flops
 Avoiding using internally generated clock signals

25. Guidelines for Resets
 The basic design issues of resets are
 Asynchronous or synchronous?
 An internal or external power-on reset?
 More than one reset, hard vs. soft reset?
 Asynchronous reset
 Hard to implement and Does not require a free-running clock
 Makes STA more difficult
 Makes the automatic insertion of test structure more difficult
 Synchronous reset
 easy to implement
 Requires a free-running clock

26. Guidelines for Resets
 The basic writing styles
 The reset signal should be a direct clear of all flip-flops

27. Partitioning for Synthesis
 Keep related logic within the same module

28. Cntd..
 For good synthesis
 Register all outputs
 Locate related combinational logic in same module
 Do not use Glue logic in top module
 Separate module that have different design goals