The document discusses Complex Instruction Set Computers (CISC) and their advantages over Reduced Instruction Set Computers (RISC). CISC processors use complex instructions that can perform multiple operations like loading from memory, arithmetic, and storing in a single instruction. This reduces the number of instructions per program at the cost of multiple clock cycles per instruction. In contrast, RISC processors use simpler single-cycle instructions, increasing the number of instructions but reducing clock cycles per instruction. There is ongoing debate about the performance of CISC vs RISC architectures as they incorporate each other's features over time.

1. PRESENTED BY
ANUSHA JANI
YASH MEHTA

2.  A complex inst ruct ion set comput er
(CI SC, pronounced like "sisk") is a
microprocessor inst ruct ion set
archit ect ure (I SA) in which each
inst ruct ion can execut e several low-
level operat ions, such as a load f rom
memory, an arit hmet ic operat ion, and
a memory st ore, all in a single
inst ruct ion. 2

3.  The philosophy behind it is, t hat
har dwar e is always f ast er t han
sof t war e, t heref or e one should make a
powerf ul inst r uct ion set , which
provides programmer s wit h assembly
inst r uct ions t o do a lot wit h shor t
programs.
 So t he pr imar y goal of t he Cisc is t o
complet e a t ask in f ew lines of
assembly inst ruct ion as possible.
3

4. Memory in t hose days was expensive
 bigger program->more st orage-
>more money
Hence needed t o reducethenumberofinstructionsperprogram
Number of inst ruct ions are reduced by
having multipleoperations
wit hin a single inst ruct ion
Mult iple operat ions lead t o many
dif f erent kinds of inst ruct ions t hat
access memory
 I n t urn making inst ruct ion lengt h
variable and f et ch-decodeexecut e
t ime unpredict able – making it more 4

5. 5
 Usemicrocode
• Used a simplified microcode instruction
set to control the data path logic. This
type of implementation is known as a
micro programmed implementation.
 Build rich instruction sets
• Consequences of using a micro
programmed design is that designers
could build more functionality into each
instruction.
 Build high-level instruction sets
• The logical next step was to build

6.  Regist er t o regist er, regist er t o
memory, and memory t o regist er
commands.
 Uses Mult iple addressing modes .
 Variable lengt h inst ruct ions where t he
lengt h of t en varies according t o t he
addressing mode
 I nst ruct ions which require mult iple
clock cycles t o execut e.
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General purpose registers
Arithmetic Logical Unit
Main memory
Memory (1,1) .. (6,4) = 24 locations
Registers: A,B,C,D,E,F
Execution unit : arithmetic ( + -* ÷)

8.  Let ' s say we want t o
f ind t he product of
t wo numbers - one
st ored in locat ion 2:3
and anot her st ored in
locat ion 5:2 - and
t hen st ore t he
product back in t he
locat ion 2:3.
 i.e.,
8
2,3
5,2

9. For t his part icular t ask, a CI SC
 processor would come prepared wit h a specif ic
inst ruct ion (we' ll call it "MULT").
MULT A,B
When execut ed, t his inst ruct ion
 loads t he t wo values int o separ at e r egist ers,
 mult iplies t he operands in t he execut ion unit , and
t hen
 st or es t he product in t he appr opr iat e regist er .
Thus, t he ent ire t ask of mult iplying t wo numbers can
be complet ed wit h one inst r uct ion
 MULT is what is known as a "complex inst ruct ion."
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I t operat es direct ly on t he
comput er' s memory banks and does
not require t he programmer t o
explicit ly call any loading or st oring
f unct ions.
I t closely resembles a command in
a higher level language,ident ical t o
t he C st at ement "a = a * b."minimizes t he number of inst ruct ions
per program (2)
sacrif icing t he number of cycles per
inst ruct ion. (1)

11.  RI SC processors only use simple inst ruct ions
t hat can be execut ed wit hin one clock cycle.
 The "MULT" command described above could be
divided int o t hree separat e commands:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B ("PROD,"f inds t he product
of t wo operands )
STORE 2:3, A ("STORE,“ moves dat a f rom a
regist er t o t he memory
banks)
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(LOAD, which moves dat a
f rom t he memory bank t o a
regist er)

12.  Primar y goal is t o
complet e a t ask in as
f ew lines of
assembly as possible
 Emphasis on
har dwar e
 I ncludes mult i-clock
complex inst r uct ions
 Memor y-t o-memor y:
"LOAD" and
"STORE"
incor porat ed in
inst ruct ions
 Pr imary goal is t o
speedup individual
inst r uct ion
 Emphasis on
sof t war e
 Single-clock,
r educed inst r uct ion
only
 Regist er t o r egist er :
"LOAD" and
"STORE"
are independent
inst r uct ions 12

13. The f ollowing equat ion is commonly used f or
expressing a comput er' s perf ormance abilit y:
Risc
The CI SC approach at t empt s t o minimize t he
number of inst ruct ions per program, sacrif icing
t he number of cycles per inst ruct ion.
RI SC does t he opposit e, reducing t he cycles per
inst ruct ion at t he cost of t he number of
inst ruct ions per program.
13
cisc

14. There is st ill considerable cont roversy
among expert s about which
archit ect ure is bet t er.
Some say t hat RI SC is cheaper and
f ast er and t heref ore t he archit ect ure
of t he f ut ure.
Ot hers not e t hat by making t he
hardware simpler, RI SC put s a great er
burden on t he sof t ware. Sof t ware
needs t o become more complex.
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15. RI SC and CI SC archit ect ures are
becoming more and more alike.
 Many of t oday' s RI SC chips support
j ust as many inst ruct ions as yest erday' s
CI SC chips. The PowerPC 601, f or
example, support s more inst ruct ions t han
t he Pent ium. Yet t he 601 is considered a
RI SC chip, while t he Pent ium is
def init ely CI SC.
 Furt her more t oday' s CI SC chips use
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16. EPIC :
 The biggest t hreat f or CI SC and RI SC
might not be each ot her, but a new
t echnology called EPI C.
 EPI C st ands f or Explicitly Parallel
Instruction Computing. EPI C can do
many inst ruct ion execut ions in parallel
t o one anot her.
 EPI C is a creat ed by I nt el and is in a
way a combinat ion of bot h CI SC and
RI SC. This will in t heory allow t he
processing of Windows-based as well as
UNI X-based applicat ions by t he same
CPU.

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17.  ht t p:/ / www.pcguide.com/ ref / cpu/ arch/ int / inst
Complexit y-c.ht ml
 ht t p:/ / arst echnica.com/ cpu/ 4q99/ risc-
cisc/ rvc-1.ht ml
 ht t p:/ / www.bookrags.com/ research/ cisc-
complex-inst ruct ion-set -comput -wcs
 ht t p:/ / www.hit equest .com/ Kiss/ risc_cisc.ht m
 ht t p:/ / en.wikipedia.org/ wiki/ Complex_inst ruct i
on_set _comput er
 ht t p:/ / en.wikipedia.org/ wiki/ X86 17

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