Dr. Sudip Roy's course CSN-221 covers computer architecture and microprocessors, focusing on datapath and control, instruction cycles, and the differences between RISC and CISC architectures. Key components like the ALU, instruction set architecture, and memory hierarchy are discussed, along with the operation of control units and the importance of efficient circuit design. The document outlines the evolution of microprocessor design philosophies, emphasizing the need for optimized instruction execution through techniques like pipelining.

1. Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html
Piazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221
Dr. Sudip Roy
CSN‐221: COMPUTER ARCHITECTURE
AND MICROPROCESSORS
Computer Organization, CPU Structure and Functions
(Lecture - 5)

2. Datapath and Control:
• Datapath:
• Memory, registers, adders, ALU, and communication buses
• Each step (fetch, decode, execute, save result) requires communication (data
transfer) paths between memory, registers and ALU
• Control:
• Datapath for each step is set up by control signals that set up dataflow
directions on communication buses and select ALU and memory functions
• Control signals are generated by a control unit consisting of one or more
finite‐state machines
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Instruction
e.g., ADD A, B, C
Operator / Control Operand / Data

3. Arithmetic & Logic Unit (ALU):
 Does all the calculations for the processor
 Everything else in the computer is there to service this unit
 Handles integers
 May handle floating point (real) numbers
 May be separate FPU (math co‐processor)
 May be on chip separate FPU (486DX +)
• ALU Inputs & Outputs:
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4. What does a processor work?
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 Instruction cycle:
1. Fetch instructions
2. Interpret (decode) instructions
3. Fetch data
4. Process (Execute) data
5. Write data
Once the computer has been started
(bootstrapped) it continually executes
instructions (until the computer is
stopped)
Different instructions take different
amounts of time to execute (typically)

5. Program Counter (PC):
Sometimes called as instruction pointer (IP) or instruction address register
(IAR) or instruction counter (IC)
In most processors, the PC is incremented after fetching an instruction, and
holds the memory address of (“points to”) the next instruction that would be
executed
In a processor where this increment precedes the fetch, the PC points to the
current instruction being executed
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6. Example: Instruction Execution
• MULT x, y, product
1. Fetch the instruction code from Memory[PC]
2. Decode the instruction. This reveals that it's a multiply instruction, and that
the operands are memory locations x, y, and product.
3. Fetch x and y from memory.
4. Multiply x and y, storing the result in a CPU register.
5. Save the result from the CPU to memory location product.
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7. Instruction Cycle:
• A complete instruction consists of
operation code
addressing mode
zero or more operands
 immediately available data
(embedded within the instruction)
 the address where the data can be
found in main memory
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Fetch
Instruction
Start
Execute
Instruction
Fetch
Operand
Decode
Instruction

8. Instruction Set Architecture (ISA):
Software design
Hardware circuits
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9. Instruction Set Architecture: Software Design
Each computer CPU must be designed to accommodate and understand
instructions according to specific formats.
Examples:
All instructions must have an operation code specified
NOP no operation
TSTST test and set
 Most instructions will require one, or more, operands
 These may be (immediate) data to be used directly
 or, addresses of memory locations where data will be found (including
the address of yet another location)
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OpCode
OpCode Operand (Address)

10. Instruction Set Architecture: Software Design
Sometimes the instruction format requires a code, called the Mode,
that specifies a particular addressing format to be distinguished from
other possible formats
direct addressing
indirect addressing
indexed addressing
relative addressing
doubly indirect addressing
etc.
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OpCode Op. (Addr.)
Op. (Addr.) Mode
Mode

11. Instruction Set Architecture: Hardware Circuits
• Everything that the computer can do is the result of designing and building
devices to carry out each function – no magic!
• At the most elementary level the devices are called logic gates.
• There are many possible gate types, each perform a specific Boolean
operation (e.g. AND, OR, NOT, NAND, NOR, XOR, XNOR)
• ALL circuits, hence all functions, are defined in terms of the basic gates
• We apply Boolean Algebra and Boolean Calculus in order to design circuits
and then optimize our designs
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12. Instruction Set Architecture: Hardware Circuits
• Data is represented by various types of “signals”, including electrical,
magnetic, optical and so on.
• Data “moves” through the computer along wires that form the various bus
networks (address, data, control) and which interconnect the gates.
• Combinations of gates are called integrated circuits (IC).
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13. Instruction Set Architecture: CU (Control Unit)
• The control unit must decode instructions, set up for communication with
RAM addresses and manage the data stored in register and accumulator
storages.
• Each such (CU) operation requires separate circuitry to perform the
specialized tasks.
• It is also necessary for computer experts to have knowledge of the various
data representations to be used on the machine in order to design
components that have the desired behaviors.
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14. Instruction Set Architecture: ALU
• All instructions together are called the instruction set
• CISC complex instruction set computer
• RISC reduced instruction set computer
• Each ALU instruction requires a separate circuit, although some instructions
may incorporate the circuit logic of other instructions
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15. RISC vs. CISC:
• Most common microprocessor designs such as the Intel 80x86 and Motorola
68K series followed the CISC philosophy.
• But recent changes in software and hardware technology have forced a re‐
examination of CISC and many modern CISC processors are hybrids,
implementing many RISC principles.
• The first RISC projects came from IBM, Stanford, and UC‐Berkeley in the late
70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2
were all designed with a similar philosophy which has become known as RISC.
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16. RISC vs. CISC:
• Certain design features have been characteristic of most RISC processors:
• one cycle execution time: RISC processors have a CPI (clock per instruction) of
one cycle. This is due to the optimization of each instruction on the CPU and a
technique called PIPELINING
• pipelining: a technique that allows for simultaneous execution of parts, or
stages, of instructions to more efficiently process instructions;
• large number of registers: the RISC design philosophy generally incorporates a
larger number of registers to prevent in large amounts of interactions with
memory
CISC was developed to make compiler development simpler. It shifts most of the
burden of generating machine instructions to the processor. For example,
instead of having to make a compiler write long machine instructions to
calculate a square‐root, a CISC processor would have a built‐in ability to do this.
E.g. Pentium is considered a modern CISC processor
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17. RISC vs. CISC:
Most common microprocessor designs such as the Intel 80x86 and Motorola
68K series followed the CISC philosophy.
But recent changes in software and hardware technology have forced a re‐
examination of CISC and many modern CISC processors are hybrids,
implementing many RISC principles.
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CISC RISC
Complex instructions require multiple
cycles
Reduced instructions take 1 cycle
Many instructions can reference memory Only Load and Store instructions can
reference memory
Instructions are executed one at a time Uses pipelining to execute instructions
Few general registers Many general registers

18. RISC vs. CISC:
CISC
• ‐Effectively realizes one particular High Level Language Computer System
in HW ‐ recurring HW development costs when change needed
RISC
• ‐Allows effective realization of any High Level Language Computer System
in SW ‐ recurring SW development costs when change needed
Hybrid solutions
• ‐RISC core & CISC interface
• ‐Still has specific performance tuning
Optimal ISA
• ‐Between RISC & CISC
• ‐Few, carefully chosen, useful complex instructions
• ‐Still has complexity handling problems
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19. Memory Hierarchy in a Computer:
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Key to your Architectural Design:
Due to size of DRAM
Due to cost and wire delays (wires on‐chip cost much less, and are faster)