my assignment

1. BINDURA UNIVERSITY OF SCIENCE EDUCATION
FUCALTY OF SCIENCE EDUCATION
SURNAME TAUZENI
NAME INNOCENT
REG NUMBER B1440405
COURSE CODE CS006
COURSE NARATION COMPUTER ARCHITECTURE
LVEL 2.1
YEAR 2015
LECTURER MRS MAJONI

2. 1. The structure of a CPU at the level of register, buses and functional
units
a) Register
 These are the components which are capable for storing data and information.
 Their function is similar to main memory are temporary storage.
 They are designed to be nearer to the control units and ALU.
 They provide faster access to data and instructions than main memory because of
their design.
REGISTERS
MAIN
MEMORY Cache
Memory
Registers
Registers
Processor

3. b) Buses
Can be defined as a data and information highway and can be classified into several types of
buses. These are: Data bus, Address bus and control bus
BUSES CONNECTINGS
BUS
BUS
BUS
i. Data Bus
 It is a set of wires that provide path for data to be transmitted from memory to the
processor.
 In computer terminology it represents a physical connection used to carry a signal
from one point to another
 It allows data to be carried in either direction.
 It is the number of bits that can be carried at once
CPU
MAIN
MEMORY
INPUT OR
OUTPUT
Input OR Output

4.  The data bus is used for retrieving information from main memory or Input or Output
to the microprocessor, or store the information from the microprocessor to memory
or Input or Output.
 Data can be moved one bit at a time or hundreds bits at a time. The width of the data
bus determines how many bits are moved at each time.
 The common width of the data bus ranges from 8 bit to 32 bit. Some advanced
microprocessors have 64 or even 128 bit wide data bus.
ii. Address bus
 This is a path which carries address issued by control unit
 Every memory cell has a unique address to be identified with
 The address bus unidirectional.
 A 32-bit computer has 32 address line
 16-lines to carry 16-bit address to memory and 16-bits to control.
 The signals on the address bus always go from CPU to memory or Input or Output.
 The information for computation is stored in memory. Some information for
computation is obtained from input ports.
 Only one of the memory Input or Output or components can respond to the CPU’s
request at each time.

iii. Control Bus
 It carries control signal issued by the processor to memory, input or output
 For example control signal are read and write instruction.
 The control bus is responsible for transmitting task commands to the memory and
Input or Output and receiving corresponding responses from memory and Input
or Output components.
 Control bus is a set of wires to carry the command from to memory or Input or
Output and to receive response or request information from memory or Input or
Output
 The number of wires on control bus depends on the complexity of the system.
c) Functional Units

5. 2. The fetch execute cycle and the steps for executions
Fetch execute
 The control unit issues signals to identify a particular area of memory.
 it reads the illustrations of the contents of memory whose address is given.
Input
Output
Memory
Instr1
Instr2
Instr3
Data1
Data2
Arithmetic
& Logic
Control
Input unit accepts
Information: Human
operators,
Electromechanical devices
other computers
Output unit sends results
of processing: To a
monitor display, to a
printer
Stores information:
Instructions, Data
Arithmetic and logic unit (ALU):
Performs the desired Operations on
the input Information as determined
by instructions in the memory
Control unit coordinates various
actions
 Input,
• Output
• Processing

6.  Fetching of instructions from main memory takes place almost at the same time as
fetching of data from memory.
 The data is stored in the accumulator registers.
 Instruction inside the instruction register and data in the accumulator register are
transferred to separate registers.
 The control unit then issues instructions to ALU execution to take place.
FETCHEXECUTE CYCLE
• Fetch
The next instruction must be located, moved across at least one system bus to the processor
This model assumes a simple fetch as our memory length all fits as a single unit in our registers.
Some processors make use of a queue to “preload” instructions. This speeds up execution as
memory is slower than the CPU and many cycles are wasted waiting for instructions to arrive.
• Execute
The instruction must be carried out, this often requires information be moved around in one or
more registers and system memory.
START Fetch
Illustration
Interpret
Instruction
EXECUTE STOP

7. The meaning of RISC and CISC and the differences betweenthem
RISC stands for Reduced Instruction Set Computer.
 RISC processors only use simple instructions that can be executed within one clock
cycle. Thus, the MULT command described above could be divided into three separate
commands:
 These are LOAD which moves data from the memory bank to a register, PROD which
finds the product of two operands located within the registers, and STORE which moves
data from a register to the memory banks.
CISC stands for Complex Instruction Set computer
 Is a process or design where single instructions can execute several low level operation
(such as a load from memory and arithmetic operation
 The primary goal of CISC architecture is to complete a task in as few lines of assembly
as possible.
 This is achieved by building processor hardware that is capable of understanding and
executing a series of operations
 For this particular task, a CISC processor would come prepared with a specific
instruction (we'll call it "MULT").
 When executed, this instruction loads the two values into separate registers, multiplies the
operands in the execution unit, and then stores the product in the appropriate register.
 Thus, the entire task of multiplying two numbers can be completed with one instruction:

8. RISC CISC
 Single word
 Emphasis on software
 Variable length
 Emphasis on hardware
 Fixed-field decoding
 Single-clock
 Variable format
 Includes multi-clock
 Load or store architecture
 Register to register:
load and store
 Memory operand
 Memory-to-memory:
load and store
 Simple operations
 are independent instructions
 Complex operations
 incorporated in instructions
3. Purposes:
a. Programcounter
 It is also register that contains the address (location) after instruction being executed
at the current time.
 As each instruction get fetched, the program counter increase its stored values by one.
 After each instruction is fetched the program counter points to the next instruction in
the sequence.
 When computer restarts or is reset, the program counter normally reverts to O
b. Memory Address Register
 The amount of memory that can be addressed by a given address can be
calculated.
 An 8-bit computer has 16-address lines. Eight of them carry 8-bit address
from processor to a memory location and the other 8-bits carry address from
memory back to processor.
 One address line can directly address two possible memory locations.
 The possible locations can either be 0 or 1.
c. The Accumulator
 The accumulator holds arithmetic data for example during processing accumulator stores
8 bits while the other 8 bits could be stored by one of the general purpose registers.
 The results of arithmetic operations are also stored in the accumulator.
 In short the accumulator supplies the ALU with data and is also supplied with results of
current processing.

9. 4. Von Neumann Architecture
I. Purposes
The computer repeatedly performs the following cycle of events;
 Fetch an instruction from memory.
 Fetch any data required by the instruction from memory.
 Execute the instruction (process the data).
 Store results in memory.
 Data and Program are stored in the same space (Memory)
 Thus, the machine can alter its own program or data –This is the
 property that makes computer viruses possible
 Conditional go to’s to other points in the program
 First real general purpose computer is a Von Neumann machine
II. Solution to alleviate
 Changing the program of a fixed-program machine requires rewiring, restructuring, or
re-designing the machine because the earliest were not so much programmed as they
were designed
 Index registers and index address become usual features of machine architecture.
.