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Cortex M
ARM Core Cortex
M0[2]
Cortex
M0+[3]
Cortex
M1[4]
Cortex
M3[5]
Cortex
M4[6]
Cortex
M7[7]
Cortex
M23[8]
Cortex
M33[12]
Cortex
M35P
Memory Protection
Unit (MPU)
No
Optional
(0,8)
No
Optional
(0,8)
Optional
(0,8)
Optional
(0,8,16)
Optional
(0,4,8,12,16)
Optional
(0,4,8,12,16)
Optional
*](https://image.slidesharecdn.com/memoryprotectionunitmpu1-201019143644/75/Memory-protection-unit-13-2048.jpg)
Uploaded byGlobalLogic Ukraine
Memory protection unit
The document outlines the functionality and advantages of a Memory Protection Unit (MPU) in real-time operating systems (RTOS), contrasting it with a Memory Management Unit (MMU) and discussing various types of memory protection. Key topics include protecting against buffer overflows, stack overflows, and access violations, as well as specific MPU features in ARM Cortex-M processors. Additionally, it describes custom MPU support for enhanced stack protection and memory management strategies in RTOS environments.
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Memory protection unit
- 1.
- 2. 2 Memory Protection Unit(MPU) Andriy Petlovanyy Senior Solution Architect October 2020
- 3. 3 Agenda • Introduction • Whatto protect? • MPU is not MMU • RTOS without MPU • RTOS with MPU • Custom MPU Support
- 4. 4 Andriy Petlovanyy • SeniorSolution Architect at GlobalLogic == 15 months • In IT > 19 years • Co-founder of
- 5.
- 6. 6 What to protect? •Buffer overflow • Stack overflow • Access violation • Executing code from stack
- 7. 7 Buffer Overflow • Memorytype - static - stack • Protection - extra parameters of function • snprintf • memcpy_s - size assertions
- 8. 8 Stack Overflow • Causes -deep call stack - recursions • Protection - Cortex M33 • stack limit register
- 9. 9 Access Violation • Causes -overflows - “wild” pointers - bit flipping (for external devices) • Protection - CRC - Inverse copies • Debugging is hard
- 10.
- 11. 11 MPU • trimmed MMU •only memory protection • low power CPU • memory regions • MemFault • ARM Core peripheral
- 12. 12 MPU • ARMv8-M upto 16 regions • 8 sub-regions (equal size) • alignment to size of region (power of 2) • Privileged => Unprivileged • Unprivileged ! => Privileged
- 13. 13 Cortex M ARM CoreCortex M0[2] Cortex M0+[3] Cortex M1[4] Cortex M3[5] Cortex M4[6] Cortex M7[7] Cortex M23[8] Cortex M33[12] Cortex M35P Memory Protection Unit (MPU) No Optional (0,8) No Optional (0,8) Optional (0,8) Optional (0,8,16) Optional (0,4,8,12,16) Optional (0,4,8,12,16) Optional *
- 14.
- 15. 15 Stack • Verify SPvalue • Stack canaries Stack #1 Stack #2 Stack #3 Stack #4
- 16. 16 Memory • Special instructionon - unused memory - null pointer address
- 17.
- 18. 18 Red Zones • MPUprotected parts • Similar to canaries Stack #1 Stack #2 Stack #3 Stack #4
- 19. 19 • Unprivileged taskscan - access their own stack - up to three user memory regions • Kernel in protected region of Flash • Calling an API function causes a temporary switch to Privilege mode FreeRTOS
- 20.
- 21. 21 What • Stack protection •Private RAM regions
- 22. 22 Stack Protection Overview •Using Cortex M4 native feature • Give access to thread to its own stack • Protect modification of code from other processes
- 23. 23 Stack Protection Zone1 • Whole Internal RAM is covered • Read permission • Priority 0 • Allow all threads to access memory on Read
- 24. 24 Stack Protection Zone2 • Read & Write permission • Priority 1 • Allow Interruptions to access stack • Allow modification of global data
- 25. 25 Stack Protection Zone3 • Read & Write permission • Priority 2 • Allow thread to use it’s stack • Disallow to access neighbor’s stacks • Is changed during context switch
- 26. 26 Tool for MPURegisters • Rearrangement of stacks to fulfill MPU specs • Stack size realigned to 512 Bytes • Allow recalculation in case of resizing
- 27.
- 28. 28 Summary • Powerful hardwarefeature • Improve fixing time for hard to tackle issues • Immediate detection of stack memory corruption • Precise location of “intruder” to memory space
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