This webinar by Andriy Petlovanyy (Senior Solution Architect, Consultant, GlobalLogic) was delivered at Embedded Community Webinar #5 on October 8, 2020. This report focuses on the use of the Memory Protection Unit (MPU) in the Cortex M series of microcontrollers. We have considered the different uses of this tool, including the strengths and weaknesses of each of the proposed approaches. Participants briefly looked at the use of MPU in various real-time operating systems (Real-Time Operating System, RTOS). The speaker shared the results of research and interesting observations in this area. More details and presentation: https://www.globallogic.com/ua/about/events/embedded-community-webinar-5/

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Memory Protection Unit (MPU)
Andriy Petlovanyy
Senior Solution Architect
October 2020

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Agenda
• Introduction
• What to protect?
• MPU is not MMU
• RTOS without MPU
• RTOS with MPU
• Custom MPU Support

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Andriy Petlovanyy
• Senior Solution Architect at GlobalLogic
== 15 months
• In IT
> 19 years
• Co-founder of

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What to protect?

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What to protect?
• Buffer overflow
• Stack overflow
• Access violation
• Executing code from stack

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Buffer Overflow
• Memory type
- static
- stack
• Protection
- extra parameters of function
• snprintf
• memcpy_s
- size assertions

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Stack Overflow
• Causes
- deep call stack
- recursions
• Protection
- Cortex M33
• stack limit register

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Access Violation
• Causes
- overflows
- “wild” pointers
- bit flipping (for external devices)
• Protection
- CRC
- Inverse copies
• Debugging is hard

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MPU is not MMU

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MPU
• trimmed MMU
• only memory protection
• low power CPU
• memory regions
• MemFault
• ARM Core peripheral

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MPU
• ARMv8-M up to 16 regions
• 8 sub-regions (equal size)
• alignment to size of region (power of 2)
• Privileged => Unprivileged
• Unprivileged ! => Privileged

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Cortex M
ARM Core Cortex
M0[2]
Cortex
M0+[3]
Cortex
M1[4]
Cortex
M3[5]
Cortex
M4[6]
Cortex
M7[7]
Cortex
M23[8]
Cortex
M33[12]
Cortex
M35P
Memory Protection
Unit (MPU)
No
Optional
(0,8)
No
Optional
(0,8)
Optional
(0,8)
Optional
(0,8,16)
Optional
(0,4,8,12,16)
Optional
(0,4,8,12,16)
Optional
*

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RTOS without MPU

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Stack
• Verify SP value
• Stack canaries
Stack #1
Stack #2
Stack #3
Stack #4

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Memory
• Special instruction on
- unused memory
- null pointer address

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RTOS with MPU

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Red Zones
• MPU protected parts
• Similar to canaries
Stack #1
Stack #2
Stack #3
Stack #4

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• Unprivileged tasks can
- access their own stack
- up to three user memory regions
• Kernel in protected region of
Flash
• Calling an API function causes a
temporary switch to Privilege
mode
FreeRTOS

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Custom MPU Support

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What
• Stack protection
• Private RAM regions

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Stack Protection Overview
• Using Cortex M4 native feature
• Give access to thread to its own
stack
• Protect modification of code from
other processes

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Stack Protection Zone 1
• Whole Internal RAM is covered
• Read permission
• Priority 0
• Allow all threads to access memory
on Read

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Stack Protection Zone 2
• Read & Write permission
• Priority 1
• Allow Interruptions to access stack
• Allow modification of global data

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Stack Protection Zone 3
• Read & Write permission
• Priority 2
• Allow thread to use it’s stack
• Disallow to access neighbor’s
stacks
• Is changed during context switch

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Tool for MPU Registers
• Rearrangement of stacks to fulfill
MPU specs
• Stack size realigned to 512 Bytes
• Allow recalculation in case of
resizing

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Summary
• Powerful hardware feature
• Improve fixing time for hard to tackle issues
• Immediate detection of stack memory corruption
• Precise location of “intruder” to memory space

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Thank you

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