Pipelining allows multiple instructions to be processed simultaneously by splitting the fetch-decode-execute cycle into stages so different instructions can be at different stages. Array or vector processors can perform the same operation on multiple data elements in parallel using multiple ALUs. Parallel processing can happen at different levels from pipelining within a CPU to multi-core and multiprocessor systems that distribute work across CPUs. RISC processors use simpler instructions that can complete in one cycle while CISC processors have more complex instructions implemented in hardware.

1. PIPELINING, PROCESSORS,
RISC AND CISC. (PPRC)
F453 COMPUTER SCIENCE 3.3.3 COMPUTER ARCHITECTURES

2. PIPELINING
• The main idea behind pipelining, is to allow multiple programs
to use the FDE cycle at one time.
• In the FDE cycle, there are 3 main processes, Fetch, Decode,
Execute.
• Each one of these 3 sections, use only 1 part of the processor
at a time.
• When 1 instruction is ‘executed’, it goes through all 3 sections
one after another, which always leaves parts of the processor
inactive.

3. DIAGRAM
• In this diagram, when the program is started, instruction 1
starts in F, then moves to D, when instruction 1 moves,
instruction 2 moves into F. This continues with all subsequent
instructions as well, and maximises processor use.Fetch Decode Execute
Instruction 1
Instruction 2 Instruction 1
Instruction 3 Instruction 2 Instruction 1
Instruction 4 Instruction 3 Instruction 2
Instruction 5 Instruction 4 Instruction 3
Instruction 6 Instruction 5 Instruction 4
Instruction 7 Instruction 6 Instruction 5

4. ARRAY OR VECTOR PROCESSING
• Some types of data can be processed individually of each other,
for example processing pixels on a screen.
• For example, if you wanted to make all red pixels blue, and all
blue pixels green, and leave green pixels alone.
• A sequential processor would examine each pixel one at a time,
and apply the change.

5. ARRAY OR VECTOR PROCESSING
• But the data for this process can be arranged into an array, like
this:
• {element 1, element 2, …}
• This is known as a one dimensional array or vector, another
type of array looks like this:
• {element 1, element 2
• Element 3, element 4}
• This is called a two dimensional array or matrix, which is
fundamental to graphics work.

6. ARRAY PROCESSOR
• An array (vector) processor has a number of ALU’s that allow all
the elements of an array to be processed at the same time.
• With an array processor, a single instruction is issued by a
control unit, and that instruction is applied to a number of data
sets at the same time.
• An array processor is a single instruction multiple data
computer (SIMD).

7. DIAGRAM
Control unit
ALU 1
ALU 3 ALU 4
ALU 2
DAT
A
DAT
A
DAT
A
DAT
A

8. MULTIPLE PROCESSORS
• The next level of parallel processing, is to have multiple
instructions acting upon multiple data sets.
• This is achieved by having a number of CPU’s being applied to
a single problem, with each CPU carrying out part of the overall
problem.

9. DIAGRAM
Job Scheduler
CPU 1
CPU 3 CPU 4
CPU 2
DAT
A
DAT
A
DAT
A
DAT
A

10. MULTIPLE PROCESSORS
• A good example of this architecture, is a supercomputer. For
example the IBM Blue Gene supercomputer has 4098
processors, allowing a lot of processing. It is used to solve
complex problems, such as predicting climate change, or
running simulations (any large problem that can be broken
down into smaller problems).
• But even normal CPU chips in personal computers will normally
have multiple cores, for example your (my) Toshiba laptop has
quad core processing ( ͡° ͜ʖ ͡°).
• A multi-core computer is a multiple instruction multiple data

11. TYPES OF PARALLEL PROCESSING
• There are a number of ways to carry out parallel processing:
Types of parallel
processing
Class of computer Application
Pipeline Single instruction
single data (SISD)
Inside a CPU
Array processor SIMD Graphics card, games
consoles
Multi-core MIMD Super computers,
modern multi-core
chips

12. ADVANTAGES AND DISADVANTAGES OF
PARALLEL PROCESSING
• Advantages of parallel processing (over Von Neumann
architecture):
• Faster when handling large amounts of data, with each data set requiring
the same processing.
• Is not limited by the bus transfer rate (Von Neumann bottleneck).
• Can make maximum use of the CPU (pipeline method) in spite of the
bottleneck.
• Disadvantages:
• Only certain types of data are suitable for parallel processing. Data that
relies on the result of a previous operation cannot be made parallel. For
parallel processing, each data set must be independent of each other.

13. CO PROCESSOR
• So far, we have discussed parallel processing as a means of
speeding up data processing. This is fine, but it does make an
assumption that the ALU within the CPU is perfect for handling
all kinds of data. And this is not always true.
• There are two basic ways of doing calculations within a CPU:
• Integer maths which only deal with whole numbers.

14. RISC AND CISC
• CISC stands for complex instruction set computers, and RISC
stands for reduced instruction set computers, and they both
describe the thought behind designing a new computer chip.
• Until recently, most chips were made using the CISC approach.
Each iteration of their computer chips offered larger and richer
instruction sets than the last one. But now chips are being
created using the RISC approach.

15. CISC
• In a CISC chip, a single instruction such as MULT a,b is
available. The chip-maker adds more complex circuits within
the CPU to carry out these instructions. So the trade-off is
more complex hardware to support simpler software coding.
• The compiler when seeing a MULT command written in a high
level language source code, can generate a single machine
code instruction to carry out the task.

16. RISC
• In a RISC chip, it is the other way round (keep the hardware
simple and let the software be more complicated). There may
be no single MULT instruction available, so the compiler has to
generate more line of codes, such as multiple ADD commands.
• But each of those instructions can be carried out in a single
cycle. You can also use the pipeline method to speed it up even
more (since a and b do not depend on each other). So overall
the RISC approach may be faster.