The document discusses ROS (Robot Operating System) integration with FPGA using cReComp and Scrp. cReComp is a tool that allows creating reusable FPGA components from C++ or HDL code. Scrp is a domain specific language used to specify the hardware and software interface of a component. The document demonstrates creating a sensor component with cReComp and evaluates its performance and timing.

1. PEAR-LAB Utsunomiya Univ.
FPGA
ROS
2016/5/25 60 r (SCI’16) 1

2. PEAR-LAB Utsunomiya Univ.
• pr
•
FPGA*
• p & [1]
*Field Programmable GateArray : LSI
FPGA
• HW-SW FPGA
• p
• ROS Robot Operating System FPGA
• ROS p S p c
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[1] Li, F., Lin, Y., He, L., and Cong, J., “Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics,” In Proceedings of the 2004 ACM/SIGDA 12th
international symposium
on Field programmable gate arrays (pp. 42-50). ACM, 2004.

3. PEAR-LAB Utsunomiya Univ.
ROS* FPGA [2]
•
•
• ROS Publish/Subscribe
p
•
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[2] Kazushi Yamashina,Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota : “Proposal of ROS-compliant FPGA Component for Low- Power
Robotic Systems - case study on image processing application -”, Proceedings of 2nd International Workshop on FPGAs for Software
Programmers, FSP2015, pp. 62-67, 2015.
( ) FPGA ( )
ROS
Topic
Topic
ROS
node
ROS FPGA

4. PEAR-LAB Utsunomiya Univ.
HW-SW p
p →
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HWóSW
p
HDLHDL
HWóSW
p
C++
p p
ROS
C++
p
r
*
FPGA ROS node
* p …

5. PEAR-LAB Utsunomiya Univ.
ROS FPGA S
cReComp
• cReComp creator for Reconfigurable robot Component
• SoC Xilinx Zynq-7020
ARM p FPGA SoC
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6. PEAR-LAB Utsunomiya Univ.
cReComp
• p
•
•
• p HDL
• HW-SW DSL*
•
• HW-SW HDL
• HW S C++
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DSL: Domain Specific Language
HDL Hardware Description Language

7. PEAR-LAB Utsunomiya Univ.
cReComp
• p HDL
•
• r
• S (DSL)
• (HDL)
• S
(C++)
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FIFO Ctrl
Access
To FIFO
HDL
FIFO
FIFO
scrp
cReComp Input
HDL
Generate
Interface
FPGA component
DSL for cReComp
User Logic
C++
Communication
HardwareSoftware
Described by User
FILE
• FIFO p
• FIFO FIFO
• p r
FIFO p Xillybus Xillinu Xillybus IP core

8. PEAR-LAB Utsunomiya Univ.
DSL
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module_name sensor_ctl
option_port{
io,1,sig_out
}
use_fifo_32
make_32_alw{
r,32,req_in
w,32,sensor_data
}
r_cycle_32 1
rw_condition_32{
if(busy_flag && finish_flag)
}
w_cycle_32 1
wire_list{
1,busy_flag
1,finish_flag
}
sub_module_name sonic_sensor uut
assign_port sonic_sensor normal{
req=req_in
busy=busy_flag
sig=sig_out
finish=finish_flag
out_data=sensor_data
}
end
Interface
Software
(C++)
FIFO 32-bits
sig_out
use_fifo_32
FIFO
Interface
Hardware
(Verilog)
option_port
sonic_sensor
( p )
write
read
w_cycle_32
FPGA→ARM
r_cycle_32
ARM→FPGA
rw_condition_32
/
sub_module_name
p
Sensor
S
C++ make_32_alw
r
ARM processor FPGASample of Scrp
req_in
sensor_data32
32
finish_flag
busy_flag
reg_list
wire_list
Scrp : Specifier for cReComp
• cReComp
•

9. PEAR-LAB Utsunomiya Univ.
2016/5/25 60 r (SCI’16) 9
C++ HDL

10. PEAR-LAB Utsunomiya Univ.
cReComp
• cReComp
•
• r
• Programmable SoC Zynq-7020 Xilinx ARM 666MHz
• OS xillinux-1.3 Ubuntu12.04
• ROS groovy
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11. PEAR-LAB Utsunomiya Univ.
6
• FPGA 3
• C++ 1 6
• Linux 1 3
1. cReComp
2. Scrp
3.
( )
• 5
(5 4
3 2 1 )
•
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• FPGA
42
• Scrp
• 3.7 17
• cReComp 1 46
Parallax PING Ultrasonic Distance Sensor
0
3
6
9
12
15
18
0
1
2
3
4
5
cReComp Scrp
()
(5 1

12. PEAR-LAB Utsunomiya Univ.
• ROS FPGA ScReComp
•
• FPGA 42
• cReComp 1 46
• cReComp p →HDL
• p
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13. PEAR-LAB Utsunomiya Univ.
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14. PEAR-LAB Utsunomiya Univ.
cReComp
FIFO 43
14
p & 23
8
18
1 46
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15. PEAR-LAB Utsunomiya Univ.
ROS Robot Operating System
• r
ROS
• Publish( )/Subscribe( ) p
• → r
2016/5/25 60 r (SCI’16) 16
Subscriber
Publisher
Service invocationmsg Message(data)
Publish/Subscribe messaging
node
Publication
nodenode
Topic
Subscription
msg

16. PEAR-LAB Utsunomiya Univ.
Zynq Xillybus xillinux-1.3
• ARM FIFO
• FPGA( ) rd_en
2016/5/25 60 r (SCI’16) 17
Input
FIFO
Output
FIFO
Xillybus
IP core
ARM
Processor
Core
full
wr_en
data
empty
rd_en
data
AXI
bus
empty
rd_en
data
full
wr_en
data
User
Logic

17. PEAR-LAB Utsunomiya Univ.
1. cReComp
a : cReComp
b : Scrp
c : ( )
2. FPGA
d :
e :
f : FPGA
3. ROS
g : p
h : ROS
i : ROS r
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0
5
10
15
20
25
30
35
1
2
3
4
5
a b c d e f g h i
Difficulty (5 Very easy ~ 1 Very difficult) Elapsed time