The document provides an overview of the TMS320C6x architecture. It describes the TMS320C6x as a 32-bit VLIW digital signal processor introduced by Texas Instruments. Key features include its ability to execute up to 8 instructions per cycle and support for floating point operations. The architecture includes 8 functional units, internal memory, external memory interfaces, and peripherals like EDMA controllers and timers. The TMS320C6x is well suited for applications involving real-time signal processing like image and speech processing.

1. TMS320C6x ARCHITECTURE
Submitted To: Presented by:
Dr. Rajesh Mehra Shweta Tripathi
Head of Department ME Modular ECE
ECE department 161610

2. Contents
Introduction
Features of C6000 devices
Architecture
CPU and Data Paths
Functional Units
Memory Architecture
User Peripherals
Applications
Conclusion
References

3. Introduction
• TMS320C6X is the family of digital signal processor introduced by
Texas Instruments.
• The TMS320C6201 (C62x), announced in 1997, is the first member of
the C6x family of fixed-point digital signal processors.
• The TMS320C6701 (C67x) floating-point processor was introduced as
another member of the C6x family of processors.
• A C6x processor can be used as a standard general-purpose digital
signal processor programmed for a specific application. Specific-
purpose digital signal processors are the modem, echo canceler, and
others.
• The TMS320C6X is a 32 bit processor based on the VLIW
architecture.
• VLIW stands for Very Large Instruction Word.

4. Features of C6000 Devices
1. Each multiplier can perform two 16X16 bit or four 8X8 multiplies
every clock cycle.
2. The CPU executes upto 8 instructions per cycle.
3. It allows designer to develop highly effective RISC like code for fast
development time.
4. It gives code size equivalence for 8 instructions executed serially or
parallel.
5. Special communication specific instructions have been added to
address common operations in error correcting codes.
6. Bit count and rotate hardware extends support for bit level
algorithm.

5. Architecture of TMS320C6X Processor

6. Architecture
Memory and peripherals available on the chip are:
1. CPU and Data Paths
2. Functional UNITS
3. Memory
4. Peripherals

7. CPU and Data Paths

8. C.P.U.
• It consists of 8 functional units- .L1,.L2,.S1,.S2,.M1,.M2,.D1 and .D2
• 2 Functional units are multipliers and remaining 6 units are ALU.
• There are 2 data paths for the CPU.
• 2 General purpose register file (A and B) one for each data path
• Each file contain sixteen 32 bit registers for file A and B respectively(A0-A15, B0-
B15)
• These register files can be used for data, data address pointers or conditional
registers.

9. Data Paths

10. Data Paths
Internal buses include-
1. 32 bit program address bus
2. 256-bit program data bus (accommodates eight 32-bit instructions)
3. two 32-bit data address buses
4. two 64-bit data buses
5. two 64-bit store data buses

11. Functional Units
Functional Unit Operations
.L Unit(.L1 and .L2) 32/40 bit arithmetic and compare operations, left 1 or 0 bit counting for 32 bits,
normalization count for 32 and 40 bits, 32 bit logical operations , byte shifts, data
packing, unpacking 5 bit constant generation.
.S Unit(.S1 and .S2) 32 bit arithmetic operations, 32/40 bit shifts and 32 bit field operations, 32 bit logical
operations, branches, constant generation, register transfer to/ from control registers
(S2 only), byte shifts, data packing, unpacking.
.M Unit(.M1 and .M2) 16X16 multiply operations, bit expansion, bit interleaving/de interleaving, variable
shift operations, rotation
.S Unit(.S1 and .S2) 32 bit add , subtract, linear and circular address calculation, load and store
operations, 5 bit constant generation, 32 bit logical operations

12. Memory Architecture
1. L1 Memory : Internal Memory
• Cache-based Architecture
• Program Cache & Data Cache
• Size : PC(4Kbyte), DC(4Kbyte)
2. L2 Memory : Internal Memory
• Size : 64Kbyte
• Program & Data
3. L3 Memory
External Memory : It has 4 chip enable (CE) spaces CE0, CE1, CE2, CE3

13. Internal Memory

14. Memory Map Summary

15. User Peripherals
1. EDMA Controller
2. HPI
3. EMIF
4. Boot Configuration
5. Two McBSP’s
6. Interrupt Selector
7. Two 32 Bit Timers
8. Power down logic

16. User Peripherals
1. Enhanced Direct Memory Access (EDMA) Controller:
• The data between address ranges in memory gap is transferred by the EDMA
controller without intervention of CPU.
• It consists of 16 programmable channels and a RAM space to hold multiple
configuration for future transfers.
2. Host Port Interface(HPI):
• It is a parallel port by which the CPU’s memory space can be directly accessed
by a host processor.
3. External Memory Interface (EMIF):
• It supports a glueless interface to several external devices such as SBSRAM,
SDRAM, asynchronous devices, external shared memory devices.

17. User Peripherals
4. Boot Configuration:
• It includes loading in code from an external ROM space on the EMIF and
loading code through the HPI / expansion bus from an external host.
5. Multi Channel Buffered Serial Ports McBSP:
• They are 2 in numbers.
• They are based on the serial port interface.
• It can also buffer serial samples in memory automatically with the aid of the
DMA/EDMA controller.
• It has multichannel capability compatible with various networking standards.

18. User Peripherals
6. Interrupt Selector:
•The TMS320C6X peripheral set produces 16 interrupt sources and the
CPU has 12 interrupts available.
•RESET and NMI interrupts are non maskable interrupts.
• The CPU interrupts are maskable.
•The Global Interrupt Enable Bit (GIE) in the control register is set to 1 to
mask the interrupts.
•The respective bit in the Interrupt Enable (IE) register is set to 1 to
enable an interrupt.
•The interrupt Flag Register (IFR) is set when the corresponding
interrupt occurs.
•It enables to chose among 12 interrupts depending upon need and
requirement.

19. User Peripherals
7. Timer:
•There are two 32 bit general purpose timers, Timer 1 and Timer 0.
•They are use to time events, count events, general pulses, interrupt the
CPU and to send synchronization events to the DMA/EDMA controller.
8. Power Down:
•It is used for the power saving .
•It allows reducing clocking to reduce power consumption.

20. Applications
1. The design of the embedded system.
2. Real time image processing and virtual reality.
3. Speech recognition system.
4. Atmospheric modeling and finite elements analysis.

21. Conclusion
• The TMS320C6X is used for real time domain signals. Because of its
high speed it is very much in demand. Good for large instruction set
and floating point analysis.

22. References
1. Teaching Real-World DSP Using MATLAB and the TMS320C31 DSK. , Cameron H. G. Wright et.al
2. Digital Signal Processing , S. Salivahanan
3. Texas Instruments, TMS320C6X Development Support Reference Guide.
4. TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide Literature Number: SPRU733A
5. TMS320C6000 Assembly Language Tools User’s Guide
6. TMS320C6x Instruction Set, Digital Signal Processing and Applications with the C6713 and C6416 DSK By Rulph Chassaing ISBN 0-
471-69007-4 Copyright © 2005 by John Wiley & Sons, Inc.

23. Thank You