1. The document introduces RISC-V assembly, an open standard instruction set architecture based on reduced instruction set computer principles. 2. It provides an example of RISC-V assembly code that loads a byte into a register, loads an immediate value into another register, increments the second register, and stores the first register value at the address in the second register. 3. It also mentions the RARS simulator that can be used to debug RISC-V assembly code and provides a second example program.

1. RISC-V Assembly
HOUR OF CODE HONG KONG

2. Who
Peter
Just a programmer
peter@quantr.hk

3. Today
1. Introduce RISC-V ASM
2. Get start
3. Code something
4. Debug something
5. RISC-V ISA

4. RISC-V
 RISC-V (pronounced "risk-five”) is an open standard instruction
set architecture (ISA) based on established reduced instruction
set computer (RISC) principles

9. https://www.quantr.hk/asmweb

10. Example
.data
myByte1: .byte 0xab
nullByte1: .byte 0x0
nullByte2: .byte 0x0
nullByte3: .byte 0x0
myByte2: .byte 0x0
.text
lw x11,myByte1
lui x12,0x10010
addix12,x12,0x4
sb x11,0x0(x12)

11. Simulator
RARS simulator
https://github.com/TheThirdOne/rars

12. Example 2
.data
myByte1: .byte 0x1, 0x2, 0x3, 0x0
.text
lui x16,0
lui x15,0
lui x14,%hi(myByte1)
label1:
lb x10,(x14)
add x15,x15,x10
addix14,x14,1
bne x10,x16,label1