ANALOG AND DIGITAL ELECTRONICS unit 4

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING
Instructor
D V S Ramanjaneyulu
Accredited by NBA & NAAC with “A” Grade
CS301ES : ANALOG & DIGITAL ELECTRONICS

P.KIRAN KUMAR,ECE DEPARTMENT 2
UNIT - IV

Boolean Algebra
•Developed by English Mathematician George Boole in
between 1815 -1864.
•It is described as an algebra of logic or an algebra of two
values i.e True or False.
•The term logic means a statement having binary decisions i.e
True/Yes or False/No.

Application of Boolean algebra
•It is used to perform the logical operations in digital computer.
•In digital computer True represent by ‘1’ (high voltage)and False represent by ‘0’
(low voltage)
•Logical operations are performed by logical operators. The fundamental logical
operators are:
1.AND (conjunction)
2.OR (disjunction)
3.NOT (negation/complement)
Boolean Algebra applied in computers electronic circuits. These
circuits perform Boolean operations and these are called logic circuits
or logic gates.

Operators
AND operator
•It performs logical
multiplication and denoted
by (.) dot.
X Y X.Y
0 0 0
0 1 0
1 0 0
1 1 1
OR operator NOT operator
addition and denoted by
(+) plus.
X Y X+Y
0 0 0
0 1 1
1 0 1
1 1 1
negation and denoted by
(-) bar. It operates on
single variable.
X X
0 1
1 0

Basic Theorems of Boolean Algebra

Note that theorem 1(b) is the dual of theorem 1(a) and that each step of the
proof in part (b) is the dual of its counterpart in part (a). Any dual theorem can
be similarly derived from the proof of its corresponding theorem.

Boolean Function
• A Boolean function expresses the logical relationship between binary variables and is
evaluated by determining the binary value of the expression for all possible values of
the variables.
•A Boolean function can be represented in a truth table. The number of rows in the
truth table is 2n, where n is the number of variables in the function.
•The binary combinations for the truth table are obtained from the binary numbers by
counting from 0 through 2n - 1.
By considering the possible simplification of
the function by applying some of the identities
of Boolean algebra:

Boolean Function

Canonical and Standard Forms
A Boolean function can be expressed algebraically from a given truth table
 By forming a minterm for each combination of the variables that produces a 1 in the
function and then taking the OR of all those terms.
By forming a maxterm for each combination of the variables that produces
a 0 in the function, and then form the AND of all those maxterms.
Boolean functions expressed as a sum of minterms or product of maxterms are
said to be in canonical form .
Using Minterms
Using Maxterms

• Another way to express Boolean functions is in standard form. In this configuration,
the terms that form the function may contain one, two, or any number of literals. There
are two types of standard forms: the sum of products and products of sums.
•The sum of products is a Boolean expression containing AND terms, called product
terms, with one or more literals each. The sum denotes the ORing of these terms.
• A product of sums is a Boolean expression containing OR terms, called sum terms.
Each term may have any number of literals. The product denotes the ANDing of these
terms.
• In standard SOP and POS each term of Boolean expression must contain all the
literals (with and with out bar) that has been used in Boolean expression.
• If the above condition is satisfied by the Boolean expression, that expression is
called Canonical form of Boolean expression.

Sum of Product( SOP) form Product of Sum (POS form)

Purpose of the Index
• Minterms and Maxterms are designated with an index
 The index number corresponds to a binary pattern
 The index for the minterm or maxterm, expressed as a binary number, is used to
determine whether the variable is shown in the true or complemented form
• For Minterms:
‘1’ means the variable is “Not Complemented” and
‘0’ means the variable is “Complemented”.
• For Maxterms:
‘0’ means the variable is “Not Complemented” and
‘1’ means the variable is “Complemented”.

Digital Logic Gates

Minimization of Boolean Expression
• Canonical SOP (Sum of Minterms) and POS (Product of Maxterm) is the derivation
/expansion of Boolean Expression.
•Canonical forms are not usually minimal.
• Minimization of Boolean expression is needed to simplify the Boolean expression and
thus reduce the circuitry complexity as it uses less number of gates to produce same
output that can be taken by long canonical expression.
 Two method can be applied to reduce the Boolean expression
i) Algebraic
ii) Using Karnaugh Map (K-Map).

KarnaughMap
The Karnaugh map (K-map for short), Maurice Karnaugh's 1953 refinement of
Edward Veitch's 1952 Veitch diagram, is a method to simplify Boolean algebra
expressions.
 K-Maps are a convenient way to simplify Boolean Expressions.
They can be used for up to 4 or 5 variables.
They are a visual representation of a truth table.

KarnaughMap
K-map for three variables K-map for Four variables
K-map for five variables

Truth table to K-Map (2 variable minterm)

K-Maps (2 Variables k-map contd…)

K - Map

Three Variable K-Map (Contd…)

Karnaugh Maps -Four Variable K-Map

K-Map Reduction Rule
To reduce the Boolean expression, first we have to mark pairs, quads and octets.
Pair –remove one variable
Quad –remove two variables
Octet –remove three variables
Imp –To get the optimum reduction, priority is given to octet first, then quad
and then pair.

K - Map
Redundant Term

K - Map
More than one solution

Four Variable: POS KarnaughMap

Karnaughmaps: Don’t cares
•In some cases, outputs are undefined. We “don’t care” if the logic produces a 0 or a
1. This knowledge can be used to simplify functions.
 Treat X’s like either 1’s or 0’s
 Very useful
 OK to leave some X’s uncovered

Karnaughmaps: Don’t cares

Don’t Care Conditions
In some situations, we don’t care about the value of a function for certain
combinations of the variables.
–these combinations may be impossible in certain contexts
–or the value of the function may not matter in when the combinations occur
•In such situations we say the function is incompletely specified and there are
multiple (completely specified) logic functions that can be used in the design.
–so we can select a function that gives the simplest circuit
•When constructing the terms in the simplification procedure, we can choose to
either cover or not cover the don’t care conditions.

Map Simplification with Don’t Cares

NAND Implementation of Boolean function
The NAND gate is said to be a universal gate because any logic circuit can be
implemented with it. To show that any Boolean function can be implemented with
NAND gates, we need only show that the logical operations of AND, OR, and
complement can be obtained with NAND gates alone.
A convenient way to implement a Boolean function with NAND gates is to obtain
the simplified Boolean function in terms of Boolean operators and then convert
the function to NAND logic

Two-Level Implementation
The procedure for obtaining the logic diagram from a Boolean function is as follows:
1. Simplify the function and express it in sum-of-products form.
2. Draw a NAND gate for each product term of the expression that has at least two
literals. The inputs to each NAND gate are the literals of the term. This procedure
produces a group of first-level gates.
3. Draw a single gate using the AND-invert or the invert-OR graphic symbol in the
second level, with inputs coming from outputs of first-level gates.
4. A term with a single literal requires an inverter in the first level. However, if the
single literal is complemented, it can be connected directly to an input of the second
level NAND gate.

Problem
Implement the following Boolean function with NAND gates:
F (x, y, z) = (1, 2, 3, 4, 5, 7)

Multilevel NAND Circuits
The most common procedure in the design of multilevel circuits is to express the
Boolean function in terms of AND, OR, and complement operations. The function can
then be implemented with AND and OR gates.
The general procedure for converting a multilevel AND–OR diagram into an all-
NAND diagram using mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not compensated
by another small circle along the same line, insert an inverter (a one-input NAND
gate) or complement the input literal.

Problem
Implement the following multilevel Boolean function
F = (AB + AB)(C + D)

NOR Implementation
The NOR operation is the dual of the NAND operation. Therefore, all procedures and
rules for NOR logic are the duals of the corresponding procedures and rules developed
for NAND logic. The NOR gate is another universal gate that can be used to implement
any Boolean function.

Problem
Implement the following multilevel Boolean function
F = (AB + AB)(C + D)

Exclusive‐OR (XOR) Function

XOR function implementation
XOR(a,b) = ab’ + a’b
• Straightforward: 5 gates
– 2 inverters, two 2‐input ANDs, one 2‐input OR
– 2 inverters & 3 2‐input NANDs
• Nonstraightforward:
– 4 NAND gates
XOR circuit with 4 NANDs

Adder
•The most basic arithmetic operation is the addition of two binary digits.
•This simple addition consists of four possible elementary operations: 0 + 0 = 0, 0 + 1
= 1, 1 + 0 = 1, and 1 + 1 = 10.
•The first three operations produce a sum of one digit, but when both addend bits are
equal to 1, the binary sum consists of two digits. The higher significant bit of this result
is called a carry .
•A combinational circuit that performs the addition of two bits is called a half adder .
One that performs the addition of three bits (two significant bits and a previous carry)
is a full adder .
•The names of the circuits stem from the fact that two half adders can be employed to
implement a full adder.

Half Adder

Full Adder
•Three inputs. Two are operand bits, third is Cin
• Two outputs: sum and carry
K Map for S
In a half adder the sum bit:

Full Adder
K Map for C
In a half adder the carry bit:
C = XY

Full Adder
Using two half Adders to Build a Full Adder
• Full adder functions
• Half adder functions
S =
C = XY

Full Adder
Two Half Adders (and an OR)

Subtractor
• Compute M‐N
– Add 2’s complement of N to M:
M + (2n – N)
• If M >= N, need only “one adder” and a “complemented of N” to do
the subtraction.
• If M < N, we also need to take 2’s complement of adder’s output to
produce magnitude of result
2n ‐{ M + (2n – N)} = N‐M

Adder‐Subtractor Design: (A+B) OR (A‐B)
• Output is result if A >= B; Discard carry
• Output is 2’s complement of result if B > A

Decimal Adders
•Computers or calculators that perform arithmetic operations directly in the
decimal number system represent decimal numbers in binary coded form.
• An adder for such a computer must employ arithmetic circuits that accept
coded decimal numbers and present results in the same code.
• A decimal adder requires a minimum of nine inputs and five outputs, since
four bits are required to code each decimal digit and the circuit must have an
input and output carry.
•There is a wide variety of possible decimal adder circuits, depending upon
the code used to represent the decimal digits.

8421 weighted coding scheme or BCD Code
•Inputs: 𝐴3 𝐴2 𝐴1 𝐴0 , 𝐵3 𝐵2 𝐵1 𝐵0 ,𝐶𝑖𝑛 from
previous decade.
•Output: 𝐶𝑜𝑢𝑡(carry to next decade), 𝑍3 𝑍2 𝑍1 𝑍0.
•Idea: Perform regular binary addition and then
apply a corrective procedure.

Comparing Binary and BCD Sums

Rules of BCD adder
•When the binary sum is greater than 1001, we obtain a non – valid BCD
representation.
•The addition of binary6 (0110) to the binary sum converts it to the correct
BCD representation and also produces an output carry as required.
•To distinguish them from binary 1000 and 1001, which also have a 1 in
position Z8 ,we specify further that either Z4 or Z2 must have a 1.
C=K+Z8Z4+Z8Z2

Implementation of BCD adder
• A decimal parallel adder that
adds n decimal digits needs n
BCD adder stages.
• The output carry from one stage
must be connected to the input
carry of the next higher-order
stage.

Binary Multiplier
Two bit Multiplication:
Three bit Multiplication
•Partial products are: 101 ×1, 101 ×1, and 101 ×0
• The partial product summation for n digit, base 2
numbers requires adding up to n digits (with
carries) in a column.
• n×m digit multiplication generates up to an m + n
digit result (same as decimal).

Multiplier Boolean Equations
• We can also make an n×m “block” multiplier and use that to form partial products.
• Example: 2 ×2 –The logic equations for each partial-product binary digit are shown
below:
• We need to "add" the columns to get the product bits P0, P1, P2, and P3.
•Note that some columns may generate carries.

A 2x2 binary multiplier
•The AND gates produce the partial
products.
•For a 2-bit by 2-bit multiplier, we can just
use two half adders to sum the partial
products. In general, though, we’ll need full
adders.
•Here C3-C0are the product, not carries!

Multiplication: a special case
•In decimal, an easy way to multiply by 10 is to shift all the digits to the left,
and tack a 0 to the right end.
128x 10 = 1280
•We can do the same thing in binary. Shifting left is equivalent to
multiplying by 2:
11x 10 = 110(in decimal, 3 x 2 = 6)
•Shifting left twice is equivalent to multiplying by 4:
11x 100 = 1100(in decimal, 3 x 4 = 12)
•As an aside, shifting to the rightis equivalent to dividingby 2.
110÷10 = 11(in decimal, 6 ÷2 = 3)

Two-Bit Comparator

Equality Comparator
4-Bit Equality Comparator

Magnitude Comparator
A > B = A3 . B3’
+ C3 . A2 . B2’
+ C3 . C2 . A1 . B1’
+ C3 . C2 . C1 . A0 . B0’
A < B = A3’ . B3
+ C3 . A2’ . B2
+ C3 . C2 . A1’ . B1
+ C3 . C2 . C1 . A0’ . B0

Decoders
• A decoder is a logic circuit that accepts a set of inputs that represents a binary
number and activates only the output that corresponds to the input number.
• In other words, a decoder circuit looks at its inputs, determines which binary
number is present there, and activates the one output that corresponds to that
number; all other outputs remain in active
• In its general form, a decoder has N input lines to handle N bits and form one to 2N
output lines to indicate the presence of one or more N-bit combinations.
The basic binary function
• An AND gate can be used as the basic decoding element because it produces a
HIGH output only when all inputs are HIGH

Decoders
Decoding logic for the binary code 1001 with an active-HIGH output.

Decoder
General decoder diagram
# There are 2N possible input combinations, from A0to AN-1.
For each of these input combinations only one of the M outputs will be active
HIGH (1), all the other outputs are LOW (0).

Decoder
• If an active - LOW output (74138, one of the output will low and the rest
will be high) is required for each decoded number, the entire decoder can
be implemented with
1. NAND gates
2. Inverters
• If an active – HIGH output (74139, one of the output will high and the
rest will be low) is required for each decoded number, the entire decoder
can be implemented with
1. AND gates
2. Inverters

2-to-4-Line Decoder
(with Enable input)-Active LOW output (1)...

2-to-4-Line Decoder
(with Enable input)-Active LOW output (2)
• The circuit operates with complemented outputs and a complement enable
input. The decoder is enabled when E is equal to 0.
• Only one output can be equal to 0 at any given time, all other outputs are
equal to 1.
•The output whose value is equal to 0 represents the minterms elected by
inputs A and B
•The circuit is disabled when E is equal to 1.

3-8 line decoder (active-HIGH)

3-8 line decoder (active-HIGH)
• This decoder can be referred to in several ways. It can be called a 3-line-to-
8-line decoder, because it has three input lines and eight output lines.
•It could also be called a binary-octal decoder or converters because it takes
a three bit binary input code and activates the one of the eight outputs
corresponding to that code. It is also referred to as a 1-of-8 decoder, because
only 1 of the 8 outputs is activated at one time.

74138 (Example of a 3 - 8 Bit Decoder)
• There is an enable function on this device, a LOW level on each input E’1,
and E’2, and a HIGH level on input E3, is required in order to make the
enable gate output HIGH.
• The enable is connected to an input of each NAND gate in the decoder, so
it must be HIGH for the NAND gate to be enabled.
•If the enable gate is not activated then all eight decoder outputs will be
HIGH regardless of the states of the three input variables A0, A1, and A2.

Logic diagram of 74138 (Example of a 3 Bit
Decoder)

Truth table of 74138 (Example of a 3 - 8 Bit
Decoder) active-LOW

4-line-to-16 line Decoder constructed with two 3-
line-to-8 line decoders
• When w=0, the top decoder is enabled and the other is disabled. The bottom
decoder outputs are all 0’s , and the top eight outputs generate min-terms 0000 to
0111.
•When w=1, the enable conditions are reversed. The bottom decoder outputs
generate min-terms 1000 to 1111, while the outputs of the top decoder are all 0’s.

Encoder
• An encoder is a combinational logic circuit that essentially performs a “reverse” of
decoder functions.
• An encoder accepts an active level on one of its inputs, representing digit, such as a
decimal or octal digits, and converts it to a coded output such as BCD or binary.
• Encoders can also be devised to encode various symbols and alphabetic characters.
• The process of converting from familiar symbols or numbers to a coded format is
called encoding.
• Most decoders accept an input code and produce a HIGH ( or a LOW) at one and
only one output line.
• In other worlds, a decoder identifies, recognizes, or detects a particular code. The
opposite of this decoding process is called encoding and is performed by a logic
circuit called an encoder.
• An encoder has a number of input lines, only one of which input is activated at a
given time and produces an N-bit output code, depending on which input is activated.

Encoder
General encoder diagram Logic circuit for octal-to binary encoder
[8-line-3-line ]

Encoder
Truth table for octal-to binary encoder [8-line-3-line ]
A low at any single input will produce the output binary code corresponding to that
input. For instance, a low at A3’ will produce O2=0, O1=1 and O0=1, which is binary
code for 3. Ao’ is not connected to the logic gates because the encoder outputs
always be normally at 000 when none of the inputs is LOW

Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder)
• A priority encoder is an encoder that includes the priority function
• If two or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.
Truth Table of a 4-input Priority Encoder:

• In addition to two outputs x, and y, the truth table has a third output
designated by V, which is a valid bit indicator that is set1 when one or more
inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal
to 0.
• X’s in the output column indicate don’t care conditions, the X’s in the input
columns are useful for representing a truth table in condensed form.
• The higher the subscript number, the higher the priority of the input. Input D3
has the highest priority, so regardless of the values of the other inputs, when
this input is 1, the output for xy is 11 (binary3)

V=D0+D1+D2+D3
K-Maps for 4-input Priority Encoder

Logic Diagram for 4-input priority encoder

MULTIPLEXERS (Data Selectors)
 A multiplexers (MUX) is a device that allows digital information from several
sources to be routed on to a single line for transmission over that line to a common
destination.
 The basic multiplexers has several data input lines and a single output line. It also
has data – select inputs, which permit digital data on any one of the inputs to be
switched to the output line.
 A modern stereo system may have a switch that selects music from one of four
sources: a cassette tape, CD, a radio tuner, or an auxiliary input such as audio from
a VCR or DVD. The switch selects one of the electronic signals from one of these
four sources and sends it to the power amplifier and speakers.
 In simple terms, this is what a multiplexer (MUX) does; it selects one of several
input signals and passes it on to the output.

Functional diagram of MUX

Two-input multiplexer

Four-input multiplexer

Logic symbol for a 1-of-4 data selector/multiplexer.

LOGIC FUNCTION GENERATION USING
MUX-Method
• An efficient method for implementing a Boolean function of n variables with a
MUX that has n-1 selection inputs and 2 n-1data inputs is given below:
–List the Boolean function in a truth table
–Apply the first n-1 variables in the table to the selection inputs of the
MUX.
–For each combination of the selection variables, evaluate the output
as a function of the last variable. This function can be 0,1, the
variable, or the complement of the variable. Apply these values to the
data inputs in the proper order.

LOGIC FUNCTION GENERATION USING MUX
Exercise 1:
Implement the logic circuit function specified in the table given below by using
74LS151 8-input data selector/multiplexer.

Solution :

Exercise 2:
Implement the Boolean function F=x’y’z +x’yz’ + xyz’ + xyz using a suitable MUX

Exercise 3:
Implement the Boolean function
F=A’B’C’D+A’B’CD+A’BC’D’+AB’CD+ABC’D’+ABC’D+ABCD’+ABCD using a
suitable MUX

Demultiplexers
 A DEMULTIPLEXER (DEMUX) basically reverses the multiplexing function.
It takes data from one line and distributes them to a given number of output
lines. For this reason, the demultiplexer is also known as a data distributor.
 A multiplexer takes several inputs and transmits one of them to the output.
 A demultiplexer (DEMUX) performs the reverse operation ; it takes a single
input and distributes it over several outputs.

General demultiplexer

A 1-line-to-4-line demultiplexer.

ANALOG AND DIGITAL ELECTRONICS unit 4

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