This document discusses advanced computational lithography techniques using flexible mask optimization (FMO). It begins with an introduction to lithography and why FMO is useful. It then describes the FMO methodology and tests conducted to demonstrate its advantages. The tests showed FMO can selectively apply advanced optical proximity correction in localized hotspots to enhance the process window while reducing mask complexity and turnaround time. FMO was able to fix defects without introducing new errors at boundaries.

1. By-
SWAMY J S
I SEM, M.TECH
VLSI AND EMBEDDED SYSTEMS
ADVANCED COMPUTATIONAL LITHOGRAPHY
TECHNIQUES USING FLEXIBLE MASK
OPTIMIZATION

2. CONTENTS
 Fabrication Process
 Introduction to Lithography
 Why FMO
 Methodology
 Tests and Results
 Advantages
 Conclusion
 References
2

3. 3
Silicon Wafer
Manufacture
Packaging
Epitaxial
Growth
Photo-
lithography
Etching
Diffusion (Ion
Implantation)
Metalization
Fabrication Processes for VLSI Devices
 Chip Fabrication Processes
oxidation

4. Lithography
4
 Lithography comes from two Greek words, “lithos” which means
stone and “graphein” which means write “ writing a pattern on
stone”
 Lithography transforms complex circuit diagrams into pattern
which are define on the wafer in a succession of exposure and
processing steps to form a number of superimposed layers of
insulator, conductor, and semiconductors materials.
 Lithography is a process that uses focused radiant energy and
chemical films that are affected by this energy to create precise
temporary patterns in silicon wafers or other materials.

5. Fig 1: Lithography Process
5

6. Types of Lithography
1. Optical Lithography
2. Electron Lithography
3. X-ray Lithography
4. Ion Lithography
6

7. Different types of Masks
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8.  Why FMO?
The 2x nm technology node, with its very low k1
values using immersion lithography is made possible by
using advanced computational lithography.
Computational techniques such as accounting for 3D
effects in OPC solvers have become essential for
addressing critical patterning issues. Although these
methods can be complex and computationally expensive,
there is a cost effective application using a framework
known as Flexible Mask Optimization(FMO)
8

9. Contd….
It would be advantageous to enable an application of
advanced OPC techniques only where necessary to repair
OPC errors and enhance the process window at limited
locations and hotspots. FMO is thus an effective framework
that can facilitate execution of OPC and verification
jobs(known as Litho Manufacturing Check or LMC) in an
iterative manner to enable correction enhancement in a
localized area based on verification results.
9

10. Fig 2: FMO Lithography
10

11.  FMO FLOW
First, when there is a need for selective are enhancement OPC job, a
gauge for hotspot processing will be generated. The FMO flow runs the
constituent jobs and related hotspot filtering rules. It usually consists of
several OPC jobs and LMC jobs running sequentially.
Thereafter, a second LMC will be deployed and hotspots are checked
after repair to assure that no additional defect was created. Mask Rule
Check(MRC) is performed for an area bigger than the repair site and
region.
An Exact Comparison Check(XOR) is carried out to ensure that the
output data outside the repair region is uncharged
Methodology
11

12. Fig 3: Flexible mask optimization framework showing OPC, LMC and FMO
contribution, interaction and handling
12

13. Repair Region
The importance of defect free boundaries and
guarantee to not generate new hotspots is of topmost
consideration for the success of good repair. Fig. 4 shows
the region definition for repair, MRC and XOR
Fig. 4. Region definitions for FMO repair, MRC and
XOR
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14.  Runtime Efficiency
The repair runtime impact on a limited area is
small compared to the full chip runtime. By enabling
the application of advanced OPC techniques only where
necessary, the overall process window will be
enhanced, the overall mask complexity is reduced and
most importantly, the total turnaround time is reduced.
14

15.  Tests and Results
The success criterion for boundary handling capability is to
verify the ability of FMO to cleanly reinsert the corrected
hotspots back into the full chip design without introducing new
defects due to proximity effects of neighboring patterns through
a rigorous regression test (as shown in Table I) and to see the
robustness of its defect-free boundary handling.
Table 1. Table of descriptions of FMO Stress tests
15

16. The success criterion for the full-chip flow
application is its usability in a manufacturing environment and
its runtime efficiency for quicker turn-around time to resolve
defects. Table II states the combination flows for FMO in a full
chip production environment.
Table 2. TABLE OF DESCRIPTIONS OF FMO FULL CHIP TEST FLOW
16

17. I. FMO boundary handling stress test results
The FMO flow has been demonstrated on multiple flows and layouts as shown
in Table I. The four test cases exhibit flows using various case studies on different types
of defects and correction methods.
In the first test case, the OPC repair was
validated on 1 mm x 1 mm metal layer clip
based on user defined hotspots as the input.
FMO is flexible enough to start repair based on
user defined hotspots rather than being restricted
to gauges from verification results only. Fig. 5
shows a snapshot of the intended repair location
and the repair box.
Fig 5. FMO defect repair at centre
and repair box boundary
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18. 18
In the second test case the FMO flow was verified using an “advanced” OPC
solution using model-based sub resolution assist features (MB-SRAF) as shown in Fig. 6.
The result demonstrates improved performance on this 2x nm node complex metal layer
using a hybrid approach of rule based sub-resolution assist features (RB-SRAF) and
model based SRAF (MB-SRAF). The “red” polygons are MB-SRAF; the “blue” polygons
are the baseline RB-SRAF while the “green” polygons are the overlap of the two OPC
solutions. The goodness of the repair has been verified and the defect was fixed after
FMO repair. The effective outcome is to achieve MB-SRAF levels of quality but at only a
slightly higher computational cost than a quick, cheap rule based approach.
Fig. 6. Verification for FMO defect repair, showing hybrid of RB-SRAF
and MB-SRAF

19. To check for robustness of the FMO repair and flow, the
third test case showcases a stress test repair. Over 330k defects
are generated by lowering the acceptable threshold for neck,
bridge and contact coverage checks. The repair box R1 depicts
the repair region and R2 represents the controlled area, where
outside of R2, the MRC and XOR must be clean. The massive
330k defect count triggers a lot of repair locations as shown in
Fig. 7. The result was promising where >99.99% of the defects
were fixed.
Fig 7.1 mm2 clip image of the FMO repair stress
test for more than 330k defects 19

20. The last test case for the FMO boundary handling stress test was to fix
the center of 3000 clips, as shown in Fig. 8. The motivation for this test case
was to stress FMO with a variety of design layouts, design densities, process
MEEF, etc. Results show that MRC and XOR (outside R2) are clean for
main, SRAF and SRIF. Fig. 9 illustrates the 2nd pass of the FMO repair for
defect with high MEEF. Additional repair on these 4 locations without any
new tuning was performed and these 4 defects were fixed successfully in a
2nd pass of FMO.
Fig 8. FMO repair stress test Fig 9. Re-Run of FMO repair for defects
for 3000 chips with high MEEF 20

21. Table 3 reiterates the four test case results. FMO
boundary handling capability was exhibited for all four test
cases on multiple flows and layouts. The ability of FMO to
cleanly reinsert the corrected hotspots back into main
design without introducing new defects due to proximity
effects of neighboring patterns has been confirmed. The
robustness of defect-free boundary handling has been
proven through rigorous regression tests
Table 3. FMO Stress Test Results
21

22. II. FMO Full Chip Test Results
Full-chip layout verification uses 2 high level categories for defects.
Those that violate a defined specification (“spec”) and those that is marginally
defective but useful for informational (“info”) purposes. The FMO full-chip test
was ran on a real device metal layer, one for neck/bridge spec defects, another
one for “tighter spec” (info) neck/bridge defects and last one for top resist bridge
type defects. The FMO capabilities of fixing the hotspots for spec defects and to
reduce the number of info defects were demonstrated.
Table 4. FMO Full Chip Test Results
22

23. One of the key challenges for immersion lithography process is
decreasing process latitude due to decreasing lithography tool focus margin.
This tool focus fluctuation has an impact on the resist pattern shape; which not
only changes wafer CD, but the resist pattern height can also decrease on
certain design layouts. An example of this using a rigorous simulator (S-Litho)
is shown in Fig. 11. The resist top-loss can cause critical defects when etched.
Thus mitigating such risk is critical for process control. FMO was used to
successfully fix these defects based on the spec for top resist bridge defects as
shown in Fig. 12.
Fig. 11. S-Litho simulation for top resist bridge Fig. 12. FMO repair for top resist bridge
defects shows bridging defect is fixed after
FMO
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24. Advantages
 Flexible Mask Optimization(FMO) enables a number of
flexible applications such as repair, insertion of known-
good libraries, efficient correction of mask revisions
 Also it helps in applying advanced OPC techniques in
highly localized areas where necessary to provide real in
production with ease
 Using FMO approach the critical patterns are corrected
with defect free boundaries
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25. Conclusion
 Conventionally, when hotspots are detected, a new recipe is required and the
full layout needs to be run to fix all of the errors. There are long runtimes
associated with reprocessing the entire layer of small number of fixes.
Moreover, making a recipe change to fix a specific problem on one design
may introduce new errors. But FMO is a good solution for all these problems.
 SARF are shown clean for all cases except the XOR non-clean case caused
by only a IDBU signal error which will be fixed in new software.
25

26. References
1. Gek Soon Chua, Yi Zou, Wei-Long Wang, Qing Yang, Shyue Fong Quek, Jianhong Qiu, Taksh
Pandey, Stanislas Baron, Sanjay Kapasi, Russel Dover, Xialong Zhang, Bo Yan, “Cost Effective
Application of Advanced Computational Lithography Techniques using Flexible Mask
Optimization”, ASMC.2013.6552743 (2013)
2. M.C. Tsai, S. Hsu, L. Chen, Y.W. Lu, J. Li, F. Chen, H. Chen, J. Tao, B.D. Chen, H. Feng, W.
Wong, W. Yuan, X. Li, Z. Li, L. Li, R. Dover, H.Y. Liu, and J. Koonmen, "Full-chip source and
mask optimization", Proc. SPIE 7973, 79730A (2011)
3. C. Beylier, N. Martin, V. Farys, F. Foussadier, E. Yesilada, F. Robert, S. Baron, R. Dover, H.Y.
Liu, “Demonstration of an effective Flexible Mask Optimization (FMO) flow”, Proc. SPIE
8326, 832616A (2012)
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27. 27

28.  Optical proximity correction (OPC) is
a photolithography enhancement technique
commonly used to compensate for image errors due
to diffraction or process effects.
 Tachyon Lithography Manufacturability Check
(LMC) is a production-proven, full-chip, full process
window, model-based verification tool that delivers the
speed and accuracy to meet the deep subwavelength
(or low k1) photolithography verification challenge of
today and tomorrow
 recipe
 something which is likely to lead to a particular
outcome.
 (commonly called k1 factor) is a coefficient that
encapsulates process-related factors.