Instruction level parallelism (ILP)

1. EC 8552 UNIT III INSTRUCTION LEVEL PARALLELISM
(ILP)
Mr. C.KARTHIKEYAN ,
ASSISTANT PROFESSOR,
ECE, RMKCET

2. INSTRUCTION LEVEL PARALLELISM (ILP)
The Parallelism among instructions

3. ILP
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB

4. Methods to increase ILP
Increase the depth of pipeline to overlap more instructions
Replicate the internal components of computer so that it can
launch multiple instructions in every pipeline stage.
- Multiple Issue

5. Multiple Issue
Static Multiple Issue Dynamic Multiple Issue
An approach to implementing a
multiple-issue processor where
many decisions are made by
the compiler before execution
There are two major ways to implement a multiple-issue processor
An approach to implementing a
multiple issue processor where
many decisions are made during
execution by the processor.
There are two primary and distinct responsibilities that must be dealt with in a
multiple-issue pipeline
1. Packaging instructions into issue slots
2. Dealing with data and control hazards

6. SPECULATION
Based on the great idea of prediction, speculation is an approach that allows
the compiler or the processor to “guess” about the properties of an
instruction, so as to enable execution to begin for other instructions that
may depend on the speculated instruction

7. SPECULATION
Software
Hardware
Compiler
Processor
The compiler usually inserts
additional instructions that check
the accuracy of the speculation
and provide a fix-up routine to use
when the speculation is incorrect
The processor usually buffers the
speculative results until it knows
they are no longer speculative

8. Static Multiple Issue Processor
issue slots The positions from which instructions could issue in
a given clock cycle
issue packet The set of instructions that issues together in one
clock cycle
Packaging of instructions done with the help of Compiler
Very Long Instruction Word (VLIW)
Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

9. Static Two Issue Processor

10. Static Two Issue Datapath

11. Simple Multiple Issue Code Scheduling

12. Loop Unrolling for Multiple-Issue Pipeline
for (i=0; i<4; i++)
{
Y[i] = A[i] * B[i];
}
for (i=0; i<2; i++)
{
Y[i] = A[i] * B[i];
Y[i+2] = A[i+2] * B[i+2];
}
for (i=0; i<100; i++)
{
Y[i] = A[i] * B[i];
}
for (i=0; i<25; i++)
{
Y[i] = A[i] * B[i];
Y[i+25] = A[i+25] * B[i+25];
Y[i+50] = A[i+50] * B[i+50];
Y[i+75] = A[i+75] * B[i+75];
}

13. Register Renaming
Used to overcome Anti-name dependency (WAR) and Output dependency (WAW)
R1 = R2 / R3
R4 = R1 * R5
R1 = R3 + R6
R3 = R1 – R4
R1 = R2 / R3
R4 = R1 * R5
R1 = R3 + R6
R3 = R1 – R4
R8
R9
R9

14. Dynamic Multiple Issue Processor
Superscalar Processor / Superscalar
An advanced pipelining technique that enables the processor to
execute more than one instruction per clock cycle by selecting
them during execution
processor decides whether zero, one, or more instructions can issue
in a given clock cycle
Compiler helps to schedule the instructions to remove dependencies

15. Dynamic Multiple Issue Processor
Dynamic Pipeline Scheduling
Hardware support for reordering the order of instruction execution so as to
avoid stalls.
Dynamic pipeline scheduling chooses which instructions to execute in a
given clock cycle while trying to avoid hazards and stalls.
lw $t0, 20($s2)
addu $t1, $t0, $t2
sub $s4, $s4, $t3
slti $t5, $s4, 20
sub $s4, $s4, $t3
lw $t0, 20($s2)
addu $t1, $t0, $t2
slti $t5, $s4, 20

16. Dynamic
Pipeline
Scheduling