The document discusses pipelining in CPU instruction execution. It describes the typical 5 stages of instruction execution: fetch, decode, execute, memory access, and write back. It shows how pipelining allows overlapping execution of multiple instructions across the stages, improving instruction throughput compared to single-cycle execution where each instruction must complete all stages before the next begins. Pipelining is implemented by dividing the CPU datapath into independent stages that each complete a part of the instruction execution process in parallel.

1. EC 8552 UNIT III PIPELINED DATA PATH
Mr. C.KARTHIKEYAN ,
ASSISTANT PROFESSOR,
ECE, RMKCET

2. PIPELINED DATA PATH
MIPS Pipeline Instruction-execution classically takes 5 steps
1. Fetch
2. Decode
3. Execute
4. Memory Access
5. Write Back
Fetch Instruction from Memory
Decode the Instruction and Read Registers
Execute the operation / Calculate an address
Access an operand in Data Memory
Write the result into a register

3. The Simple Data Path

4. IF ID EX MEM WB
IF ID EX MEM WB
Inst 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAM
INSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

5. IF ID EX MEM WB
IF ID EX MEM WB
Inst 1
Inst 2 IF ID EX MEM WB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAM
INSTRUCTIONS
Instruction 2 Instruction 2 Instruction 2 Instruction 2 Instruction 2
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

6. IF ID EX MEM WB
IF ID EX MEM WB
Inst 1
Inst 2 IF ID EX MEM WB
Inst 3 IF ID EX MEM WB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLOCK CYCLES
PROGRAM
INSTRUCTIONS
Instruction 3 Instruction 3 Instruction 3 Instruction 3 Instruction 3
EXECUTION WITHOUT PIPELINING
SINGLE CYCLE IMPLEMENTATION

7. IF ID EX MEM WB
IF ID EX MEM WB
lw $10,20($1)
IF ID EX MEM WB
IF ID EX MEM WB
1 2 3 4 5 6 7 8 9
CLOCK CYCLES
PROGRAM
INSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITH PIPELINING
IF ID EX MEM WB
IF ID EX MEM WB
Instruction 2 Instruction 2
Instruction 3 Instruction 2
Instruction 3
Instruction 4 Instruction 2
Instruction 3
Instruction 4
Instruction 5
sub $11,$2,$3
add $12,$3,$4
lw $13,24($1)
add $14,$5,$6
Pipelining improves performance by increasing instruction throughput and
decreasing the execution time of an individual instruction

8. IMPLEMENTATION OF PIPELINING
A B C A B C
Ed: log |x.y|
A  x.y, B ||, C  log ()

9. Single Cycle Implementation of Data path

10. PIPELINED VERSION OF DATA PATH

11. INSTRUCTION FETCH

12. INSTRUCTION DECODE

13. EXECUTE

14. MEMORY ACCESS

15. WRITE BACK

16. IF ID EX MEM WB
IF ID EX MEM WB
lw $10,20($1)
IF ID EX MEM WB
IF ID EX MEM WB
1 2 3 4 5 6 7 8 9
CLOCK CYCLES
PROGRAM
INSTRUCTIONS
Instruction 1 Instruction 1 Instruction 1 Instruction 1 Instruction 1
EXECUTION WITH PIPELINING
IF ID EX MEM WB
IF ID EX MEM WB
Instruction 2 Instruction 2
Instruction 3 Instruction 2
Instruction 3
Instruction 4 Instruction 2
Instruction 3
Instruction 4
Instruction 5
sub $11,$2,$3
add $12,$3,$4
lw $13,24($1)
add $14,$5,$6

17. THE SINGLE-CLOCK-CYCLE DIAGRAM CORRESPONDING TO CLOCK CYCLE 5 OF THE PIPELINE