1. Vinod P
Email id: vinuvinodp22@gmail.com
Mobile Number: 9986972308
Career Objective:
Seeking a challenging position in a well established company that offers professional growth and ample
opportunities to learn and enrich my competencies in my profession that also contributes towards
organizational growth.
Core Competency:
 Good knowledge of Verilog RTL coding and ASIC flow
 Good knowledge of System Verilog (with Regression) which overcomes the limitations of
Verilog
 Developed all testbench components like – Generator, Driver, Monitor, Scoreboard,
Environment, Testbench and Top modules for different DUVs
 Good understanding of Universal Verification Methodology
 Good knowledge of Degital design concepts
 Very good knowledge of OOP’s concept
 Practical understanding of technology, its application, implementation and verification scope
 Good exposure to technology by undergoing additional training in VLSI at RV-VLSI design
centre
 Implemented a VLSI project during my post PG diploma
 Good working knowledge on linux and windows operating system
 Tools Used : Questa Sim(Mentor Graphics)
Education :
Degree Discipline
Institute
University
Year of
Passing
Aggregate
PG Diploma VLSI
RV-VLSI Design
Center
2015
BE/B.Tech
Electronics &
Communication
Amruta Institute of
Engineering and
Management Sciences,
Bangalore
VTU
2014 61.39 %
12th
Vijaya Composite PU
College, Bangalore
Pre University Board,
Karnataka
2010 62.33 %
10th
St. Joseph’s High
School, Bangalore
SSLC Board,
Karnataka
2008 75.68 %

2. Projects:
Title : Verification of Single port RAM using System-Verilog
Role : Developing architecture and test bench
Organization: RV-VLSI
Description :
Developed a test bench in System Verilog for verifying RAM with
100% coverage and Test plan creation from Design Specification,
Self-Checking Testbench, Code Coverage, Functional Coverage,
Constrained Randomization, Regressions, Random and Directed
Testing Methodology and Corner Cases.
Tools Used : Questa sim 10.2 (Mentor Graphics)
Challenges Faced : Finding out which value of the randomized input field was not hit so
as to fix the drop in the functional coverage
Title : Verification of FIFO using System-Verilog and UVM
Role : Developing architecture and test bench
Organization: RV-VLSI
Description :
Verification of synchronous FIFO using System Verilog and UVM
methodology with maximum functional coverage. Development of
different test sequences for write, read, simultaneous write/read
operations.
Tools Used Questa sim 10.2 (Mentor Graphics)
Challenges Faced: Meeting 100 % functional coverage was a little difficult in the
beginning but was overcome finally.
Title : Verification of Mini UART using System-Verilog and UVM
Role : Developing architecture and test bench
Organization : RV-VLSI
Duration of Project : 3 weeks
Description : Functionality of the mini UART is checked using the system verilog
and UVM testbench architecture. Testcases for transmit, receive and
both transmit and receive were written with the regression testcase.
Code coverage and functional coverage for the verified design were
reported.
Tools Used : Questa sim 10.2 (Mentor Graphics)
Challenges Faced: Synchronizing the collection of the input and output data at the
scoreboard for proper comparison.

3. Personal Profile:
Name :vinod p
Date of Birth : 22/Aug/1992
Address
:#93,2nd main,3rd cross,B.U.E.H.B.C.S layout,BEML 5th
stage,Rajarajeshwarinagar ,Bangalore - 560098
Father Name : Puttaswamy
Nationality : Indian
Sex : Male
Languages known : English,Kannada and Hindi
I would hereby wish to declare that all the information furnished above are true and to the
best of my knowledge.
Date: 23-05-2015
Current Place: Bangalore VINOD P