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EC 8552 UNIT III EXCEPTIONS S
Mr. C.KARTHIKEYAN ,
ASSISTANT PROFESSOR,
ECE, RMKCET
EXCEPTIONS
Exception Vs Interrupt
EXCEPTION
INTERRUPT
Exception Vs Interrupt
Exceptions and Interrupts are unexpected events that disrupt the
normal flow of instruction execution.
An exception is an unexpected event from within the processor
that disrupts the program execution.
An interrupt is an exception that comes from outside of the
processor.
Exception Vs Interrupt
Exception Types
There are three events that will trigger an exception
1. Arithmetic overflow
2. Undefined instruction
3. System call
How Exceptions Are Handled in the MIPS
Architecture
When an exception occurs, the processor will perform the following actions:
move the current PC into another register (EPC)
record the reason for the exception in the Cause Register / Status Register
automatically disable further exceptions from occurring, by left-shifting
the Status register
change control to a hardwired exception handler address
How Exceptions Are Handled in the MIPS
Architecture
To return from a handler, The Processor may perform the following actions:
move the contents of the EPC register to the PC
re-enable exceptions, by right-shifting the Status register
How Multiple Types of Exceptions Are
Handled in the MIPS Architecture
There are two methods for handling this problem:
1. Polled interrupts
2. Vectored interrupts
Vectored Interrupt
Arithmetic Overflow
Handled by MIPS

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5. Exception.pptx

  • 1. EC 8552 UNIT III EXCEPTIONS S Mr. C.KARTHIKEYAN , ASSISTANT PROFESSOR, ECE, RMKCET
  • 4. Exception Vs Interrupt Exceptions and Interrupts are unexpected events that disrupt the normal flow of instruction execution. An exception is an unexpected event from within the processor that disrupts the program execution. An interrupt is an exception that comes from outside of the processor.
  • 6.
  • 7. Exception Types There are three events that will trigger an exception 1. Arithmetic overflow 2. Undefined instruction 3. System call
  • 8. How Exceptions Are Handled in the MIPS Architecture When an exception occurs, the processor will perform the following actions: move the current PC into another register (EPC) record the reason for the exception in the Cause Register / Status Register automatically disable further exceptions from occurring, by left-shifting the Status register change control to a hardwired exception handler address
  • 9. How Exceptions Are Handled in the MIPS Architecture To return from a handler, The Processor may perform the following actions: move the contents of the EPC register to the PC re-enable exceptions, by right-shifting the Status register
  • 10. How Multiple Types of Exceptions Are Handled in the MIPS Architecture There are two methods for handling this problem: 1. Polled interrupts 2. Vectored interrupts