2. CONTENTS
1. INTRODUCTION
2. CASES OF METASTABILITY
3. ILLUSTRATION OF METASTABILITY
4. ENTERING METASTABILITY
5. DURING METASTABILITY
6. INTRODUCTION TO MTBF
7. DERIVATION OF MTBF
8. REFERENCES
3. WHAT IS METASTABILTY
Whenever there are setup and hold time
violations in any flip-flop, it enters in a state
where its output is unpredictable
At the end of metastable state, the flip-flop
settles down to either '1' or '0'.
4. CASES OF METASTABILITY
• FOR SYNCHRONOUS SYSTEM-
When skew is present
• FOR ASYNCHRONOUS SYSEM-
Whenever setup and hold time violation occurs.
7. GRAPH B/W INPUT VOLTAGE AND TIME
Figure 2 :Charts show multiple inputs D, internal clock (CLK2) and
multiple corresponding outputs Q (voltage vs. time). The input edge is
moved in steps of 100ps, 1ps and 0.1fs in the top, middle and bottom
8. From the graph if we increase the
frequency of input signal then the
probability of system to move in
metastability will increase
period of metastability also increased
10. •The Analog model result in two first-
order differential equations that can be
combined into one, as follows:-
11. INTRODUCTION TO MTBF
MTBF is Mean time between failure
It gives us information on how often a particular
element will fail.
It gives the average time interval between two
successive failures.
12. EQUATION OF MTBF
The MTBF equation is
MTBF =
Where:
S = synchronization period
Tw, = flip-flop characteristic constants
FC= clock frequency
FD = average input rate of change
13. DERIVING MTBF EQUATION
Clearly, if meta-stability starts with V=VO and
ends when V=V1, then the time to exit meta-
stability is tm:
14. Probabilistic analysis shows that, given the fact that
a latch is metastable at time zero, the probability
that it will remain metastable at time t >0 is e-
t/τ, which diminishes exponentially fast.
The probability of entering metastability, which is
the probability of D‟s having changed within the
TW window, is TW/TC =TWFC
But D may not change every cycle; if it changes at
a rate FD, then the rate of entering metastability
becomes Rate =FDFCTW.
15. P(failure) = p(enter MS) X p(time to exit >
S)
= X
Rate(failures) = X
The inverse of the failure rate is the mean
time between failures (MTBF):
MTBF =
16. MTBF EXAMPLE
Consider an ASIC designed for a 28-nm high-
performance CMOS process. We estimate t =
10 ps, TW = 20 ps and FC = 1 GHz.
Let’s assume that data changes every 10
clock cycles at the input of our flip-flop, and
we allocate one clock cycle for resolution: S =
TC.
Plug all these into the formula and we obtain
4 X 1029 years.
17. REFERENCES
R. Ginosar, “Metastability and synchronizers:A
tutorial,” IEEE Design Test Comput., vol. 28, pp.
23–35, May 2011.
S. Lubkin, „„Asynchronous Signals in Digital
Computers,‟‟ Mathematical Tables and Other
Aids to Computation (ACM section), vol. 6, no.
40, 1952, pp. 238-241.
H.J.M. Veendrick, „„The Behavior of Flip-Flops
Used as Synchronizers and Prediction of Their
Failure Rate,‟‟ IEEE J. Solid-State Circuits, vol.
15, no. 2, 1980, pp. 169-176.