The document discusses techniques for mitigating single event upsets (SEUs) through dynamic partial reconfiguration in SRAM-based FPGAs. It aims to apply traditional fault tolerance methods like duplication with comparison and triple modular redundancy while exploiting dynamic reconfiguration. An exhaustive design space exploration is performed to identify the most promising solutions based on metrics like area overhead and fault detection properties. Completed work includes case studies on a block cipher and FIR filter. Future work involves designing an algorithm for smarter exploration of solutions using multiple techniques and implementing an automatic partial reconfiguration flow.