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3rd 3DDRESD: DReAMS

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Marco Santambrogio
Marco Santambrogio
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Design Methodologies for Dynamic Reconfigurable Multi-FPGA Systems BY Alessandro Panella [email_address] 3-Day DRESD 07/28 – 08/01 2008 Hotel Villa Gina, Goglio, Italy
About this thesis (1/2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
About this thesis (2/2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Field Programmable Gate Array ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Multi-FPGA Systems (MFS) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
MFS topologies (1/2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],PRO CON
MFS topologies (2/2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurability ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Dynamically Reconfigurable MFS’s ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Design hierarchy ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Block-to-block net Block-to-interface net
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Related works - MFS design flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Complete MFS design flows (a) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Complete MFS design flows (b) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Partial MFS design flows ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Dynamic Reconfigurable MFS ,[object Object],[object Object],[object Object],[object Object],[ Ouaiss et al. , An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA architectures, 1998] ,[object Object]
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Proposed methodology ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Design Extraction
Intermediate representation ,[object Object],[object Object],[object Object],[object Object]
VHDL Parsing ,[object Object],[object Object],[object Object]
Example Hierarchy Flattened view DES encryption core (part of the 3DES core circuit)
Static Global Layout ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Integrated P&P
Annealing implementation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Sequential P&P ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Clustering metrics ,[object Object],[object Object],[object Object],[object Object],[object Object]
Blocks reuse ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Isomorphic clusters ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Isomorphic clusters extraction (1/2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Isomorphic clusters extraction (2/2) ,[object Object],[object Object]
Blocks reuse choices ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ILP model for blocks reuse ,[object Object]
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Experiments ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Results: test circuits ,[object Object],[object Object],[object Object],[object Object]
Integrated vs. Sequential P&P (1/2) ,[object Object],NOTE : by setting the distance between any two FPGAs equal to 1, the integrated annealing approach is actually a partitioning algorithm
[object Object],[object Object],[object Object],[object Object],Integrated vs. Sequential P&P (2/2)
Clustering Vs. Metis
Results: ILP model solving Timing results ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusion: contributions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusion: future works ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The end. ,[object Object]
That’s all folks! ,[object Object],[object Object]

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3rd 3DDRESD: DReAMS

  • 1. Design Methodologies for Dynamic Reconfigurable Multi-FPGA Systems BY Alessandro Panella [email_address] 3-Day DRESD 07/28 – 08/01 2008 Hotel Villa Gina, Goglio, Italy
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  • 23. Example Hierarchy Flattened view DES encryption core (part of the 3DES core circuit)
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Editor's Notes

  1. Good morning to everybody and thank you for being here, I am… I’m going to present my thesis work, which is entitled…