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  1. 1. CIS775: Computer Architecture Chapter 1: Fundamentals of Computer Design
  2. 2. Course Objectives <ul><li>To evaluate the issues involved in choosing and designing instruction set. </li></ul><ul><li>To learn concepts behind advanced pipelining techniques. </li></ul><ul><li>To understand the “hitting the memory wall” problem and the current state-of-art in memory system design. </li></ul><ul><li>To understand the qualitative and quantitative tradeoffs in the design of modern computer systems </li></ul>
  3. 3. What is Computer Architecture? <ul><li>Functional operation of the individual HW units within a computer system, and the flow of information and control among them. </li></ul>Technology Programming Language Interface Interface Design (ISA) Measurement & Evaluation Parallelism Computer Architecture : Applications OS Hardware Organization
  4. 4. Computer Architecture Topics Instruction Set Architecture Pipelining, Hazard Resolution, Superscalar, Reordering, Prediction, Speculation, Vector, DSP Addressing, Protection, Exception Handling L1 Cache L2 Cache DRAM Disks, WORM, Tape Coherence, Bandwidth, Latency Emerging Technologies Interleaving Memories RAID VLSI Input/Output and Storage Memory Hierarchy Pipelining and Instruction Level Parallelism
  5. 5. Computer Architecture Topics M Interconnection Network S P M P M P M P ° ° ° Topologies, Routing, Bandwidth, Latency, Reliability Network Interfaces Shared Memory, Message Passing, Data Parallelism Processor-Memory-Switch Multiprocessors Networks and Interconnections
  6. 6. Measurement and Evaluation <ul><li>Architecture is an iterative process: </li></ul><ul><li>Searching the space of possible designs </li></ul><ul><li>At all levels of computer systems </li></ul>Creativity Good Ideas Mediocre Ideas Bad Ideas Cost / Performance Analysis
  7. 7. Issues for a Computer Designer <ul><li>Functional Requirements Analysis (Target) </li></ul><ul><ul><li>Scientific Computing – HiPerf floating pt. </li></ul></ul><ul><ul><li>Business – transactional support/decimal arith. </li></ul></ul><ul><ul><li>General Purpose –balanced performance for a range of tasks </li></ul></ul><ul><li>Level of software compatibility </li></ul><ul><ul><li>PL level </li></ul></ul><ul><ul><ul><li>Flexible, Need new compiler, portability an issue </li></ul></ul></ul><ul><ul><li>Binary level (x86 architecture) </li></ul></ul><ul><ul><ul><li>Little flexibility, Portability requirements minimal </li></ul></ul></ul><ul><li>OS requirements </li></ul><ul><ul><li>Address space issues, memory management, protection </li></ul></ul><ul><li>Conformance to Standards </li></ul><ul><ul><li>Languages, OS, Networks, I/O, IEEE floating pt. </li></ul></ul>
  8. 8. Computer Systems: Technology Trends <ul><li>1988 </li></ul><ul><ul><li>Supercomputers </li></ul></ul><ul><ul><li>Mas sively Par allel Processors </li></ul></ul><ul><ul><li>Mini-supercomputers </li></ul></ul><ul><ul><li>Minicomputers </li></ul></ul><ul><ul><li>Workstations </li></ul></ul><ul><ul><li>PC’s </li></ul></ul><ul><li>2002 </li></ul><ul><ul><li>Powerful PC’s and SMP Workstations </li></ul></ul><ul><ul><li>Network of SMP Workstations </li></ul></ul><ul><ul><li>Mainframes </li></ul></ul><ul><ul><li>Supercomputers </li></ul></ul><ul><ul><li>Embedded Computers </li></ul></ul>
  9. 9. Why Such Change in 10 years? <ul><li>Performance </li></ul><ul><ul><li>Technology Advances </li></ul></ul><ul><ul><ul><li>CMOS (complementary metal oxide semiconductor) VLSI dominates older technologies like TTL (transistor transistor logic) in cost AND performance </li></ul></ul></ul><ul><ul><li>Computer architecture advances improves low-end </li></ul></ul><ul><ul><ul><li>RISC, pipelining, superscalar, RAID, … </li></ul></ul></ul><ul><li>Price: Lower costs due to … </li></ul><ul><ul><li>Simpler development </li></ul></ul><ul><ul><ul><li>CMOS VLSI: smaller systems, fewer components </li></ul></ul></ul><ul><ul><li>Higher volumes </li></ul></ul><ul><ul><li>Lower margins by class of computer, due to fewer services </li></ul></ul><ul><li>Function :Rise of networking/local interconnection technology </li></ul>
  10. 10. Growth in Microprocessor Performance
  11. 11. Six Generations of DRAMs
  12. 12. Updated Technology Trends (Summary) Capacity Speed (latency) Logic 4x in 4 years 2x in 3 years DRAM 4x in 3 years 2x in 10 years Disk 4x in 2 years 2x in 10 years Network (bandwidth) 10x in 5 years <ul><li>Updates during your study period?? </li></ul><ul><ul><li>BS (4 yrs) </li></ul></ul><ul><ul><li>MS (2 yrs) </li></ul></ul><ul><ul><li>PhD (5 yrs) </li></ul></ul>
  13. 15. Performance Trends (Summary) <ul><li>Workstation performance (measured in Spec Marks) improves roughly 50% per year (2X every 18 months) </li></ul><ul><li>Improvement in cost performance estimated at 70% per year </li></ul>
  14. 16. Computer Engineering Methodology Evaluate Existing Systems for Bottlenecks Simulate New Designs and Organizations Implement Next Generation System Technology Trends Benchmarks Workloads Implementation Complexity
  15. 17. How to Quantify Performance? <ul><li>Time to run the task (ExTime) </li></ul><ul><ul><li>Execution time, response time, latency </li></ul></ul><ul><li>Tasks per day, hour, week, sec, ns … (Performance) </li></ul><ul><ul><li>Throughput, bandwidth </li></ul></ul>Plane Boeing 747 BAD/Sud Concodre Speed 610 mph 1350 mph DC to Paris 6.5 hours 3 hours Passengers 470 132 Throughput (pmph) 286,700 178,200
  16. 18. The Bottom Line: Performance and Cost or Cost and Performance? <ul><li>&quot;X is n times faster than Y&quot; means </li></ul><ul><li>ExTime(Y) Performance(X) </li></ul><ul><li>--------- = --------------- </li></ul><ul><li>ExTime(X) Performance(Y) </li></ul><ul><li>Speed of Concorde vs. Boeing 747 </li></ul><ul><li>Throughput of Boeing 747 vs. Concorde </li></ul><ul><li>Cost is also an important parameter in the equation which is why concordes are being put to pasture! </li></ul>
  17. 19. Measurement Tools <ul><li>Benchmarks, Traces, Mixes </li></ul><ul><li>Hardware: Cost, delay, area, power estimation </li></ul><ul><li>Simulation (many levels) </li></ul><ul><ul><li>ISA, RT, Gate, Circuit </li></ul></ul><ul><li>Queuing Theory </li></ul><ul><li>Rules of Thumb </li></ul><ul><li>Fundamental “Laws”/Principles </li></ul><ul><li>Understanding the limitations of any measurement tool is crucial. </li></ul>
  18. 20. Metrics of Performance Compiler Programming Language Application Datapath Control Transistors Wires Pins ISA Function Units (millions) of Instructions per second: MIPS (millions) of (FP) operations per second: MFLOP/s Cycles per second (clock rate) Megabytes per second Answers per month Operations per second
  19. 21. Cases of Benchmark Engineering <ul><li>The motivation is to tune the system to the benchmark to achieve peak performance. </li></ul><ul><li>At the architecture level </li></ul><ul><ul><li>Specialized instructions </li></ul></ul><ul><li>At the compiler level ( compiler flags ) </li></ul><ul><ul><li>Blocking in Spec89  factor of 9 speedup </li></ul></ul><ul><ul><li>Incorrect compiler optimizations/reordering. </li></ul></ul><ul><ul><li>Would work fine on benchmark but not on other programs </li></ul></ul><ul><li>I/O level </li></ul><ul><ul><li>Spec92 spreadsheet program (sp) </li></ul></ul><ul><ul><li>Companies noticed that the produced output was always out put to a file (so they stored the results in a memory buffer) and then expunged at the end (which was not measured). </li></ul></ul><ul><ul><li>One company eliminated the I/O all together. </li></ul></ul>
  20. 22. After putting in a blazing performance on the benchmark test, Sun issued a glowing press release claiming that it had outperformed Windows NT systems on the test. Pendragon president Ivan Phillips cried foul, saying the results weren't representative of real-world Java performance and that Sun had gone so far as to duplicate the test's code within Sun's Just-In-Time compiler . That's cheating, says Phillips, who claims that benchmark tests and real-world applications aren't the same thing. Did Sun issue a denial or a mea culpa? Initially, Sun neither denied optimizing for the benchmark test nor apologized for it. &quot; If the test results are not representative of real-world Java applications, then that's a problem with the benchmark ,&quot; Sun's Brian Croll said. After taking a beating in the press, though, Sun retreated and issued an apology for the optimization.[Excerpted from PC Online 1997]
  21. 23. Issues with Benchmark Engineering <ul><li>Motivated by the bottom dollar, good performance on classic suites  more customers, better sales. </li></ul><ul><li>Benchmark Engineering  Limits the longevity of benchmark suites </li></ul><ul><li>Technology and Applications  Limits the longevity of benchmark suites. </li></ul>
  22. 24. SPEC: System Performance Evaluation Cooperative <ul><li>First Round 1989 </li></ul><ul><ul><li>10 programs yielding a single number (“SPECmarks”) </li></ul></ul><ul><li>Second Round 1992 </li></ul><ul><ul><li>SPECInt92 (6 integer programs) and SPECfp92 (14 floating point programs) </li></ul></ul><ul><ul><ul><li>Compiler Flags unlimited. March 93 </li></ul></ul></ul><ul><ul><ul><li>new set of programs: SPECint95 (8 integer programs) and SPECfp95 (10 floating point) </li></ul></ul></ul><ul><ul><li>“ benchmarks useful for 3 years” </li></ul></ul><ul><ul><li>Single flag setting for all programs: SPECint_base95, SPECfp_base95 </li></ul></ul><ul><ul><li>SPEC CPU2000 (11 integer benchmarks – CINT2000, and 14 floating-point benchmarks – CFP2000 </li></ul></ul>
  23. 25. SPEC 2000 (CINT 2000)Results
  24. 26. SPEC 2000 (CFP 2000)Results
  25. 27. Reporting Performance Results <ul><li>Reproducability </li></ul><ul><li> Apply them on publicly available benchmarks. Pecking/Picking order </li></ul><ul><ul><li>Real Programs </li></ul></ul><ul><ul><li>Real Kernels </li></ul></ul><ul><ul><li>Toy Benchmarks </li></ul></ul><ul><ul><li>Synthetic Benchmarks </li></ul></ul>
  26. 28. How to Summarize Performance <ul><li>Arithmetic mean (weighted arithmetic mean) tracks execution time: sum(T i )/n or sum(W i *T i ) </li></ul><ul><li>Harmonic mean (weighted harmonic mean) of rates (e.g., MFLOPS) tracks execution time: n/sum(1/R i ) or 1/sum(W i /R i ) </li></ul><ul><li>Normalized execution time is handy for scaling performance (e.g., X times faster than SPARCstation 10) </li></ul><ul><li>But do not take the arithmetic mean of normalized execution time, use the geometric mean = (Product(R i )^1/n) </li></ul>
  27. 29. Performance Evaluation <ul><li>“ For better or worse, benchmarks shape a field” </li></ul><ul><li>Good products created when have: </li></ul><ul><ul><li>Good benchmarks </li></ul></ul><ul><ul><li>Good ways to summarize performance </li></ul></ul><ul><li>Given sales is a function in part of performance relative to competition, investment in improving product as reported by performance summary </li></ul><ul><li>If benchmarks/summary inadequate, then choose between improving product for real programs vs. improving product to get more sales; Sales almost always wins! </li></ul><ul><li>Execution time is the measure of computer performance! </li></ul>
  28. 30. Simulations <ul><li>When are simulations useful? </li></ul><ul><li>What are its limitations, I.e. what real world phenomenon does it not account for? </li></ul><ul><li>The larger the simulation trace, the less tractable the post-processing analysis. </li></ul>
  29. 31. Queueing Theory <ul><li>What are the distributions of arrival rates and values for other parameters? </li></ul><ul><li>Are they realistic? </li></ul><ul><li>What happens when the parameters or distributions are changed? </li></ul>
  30. 32. Quantitative Principles of Computer Design <ul><li>Make the Common Case Fast </li></ul><ul><ul><li>Amdahl’s Law </li></ul></ul><ul><li>CPU Performance Equation </li></ul><ul><ul><li>Clock cycle time </li></ul></ul><ul><ul><li>CPI </li></ul></ul><ul><ul><li>Instruction Count </li></ul></ul><ul><li>Principles of Locality </li></ul><ul><li>Take advantage of Parallelism </li></ul>
  31. 34. Amdahl’s Law ExTime new = ExTime old x (1 - Fraction enhanced ) + Fraction enhanced Speedup overall = ExTime old ExTime new Speedup enhanced = 1 (1 - Fraction enhanced ) + Fraction enhanced Speedup enhanced
  32. 35. Amdahl’s Law <ul><li>Floating point instructions improved to run 2X; but only 10% of actual instructions are FP </li></ul>Speedup overall = ExTime new =
  33. 36. CPU Performance Equation <ul><li> Inst Count CPI Clock Rate </li></ul><ul><li>Program X </li></ul><ul><li>Compiler X (X) </li></ul><ul><li>Inst. Set. X X </li></ul><ul><li>Organization X X </li></ul><ul><li>Technology X </li></ul>CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle
  34. 37. Cycles Per Instruction <ul><li>Invest Resources where time is Spent! </li></ul>CPU time = CycleTime *  CPI * I i = 1 n i i CPI =  CPI * F where F = I i = 1 n i i i i Instruction Count “ Instruction Frequency” <ul><li>CPI = (CPU Time * Clock Rate) / Instruction Count </li></ul><ul><ul><li>= Cycles / Instruction Count </li></ul></ul>“ Average Cycles per Instruction”
  35. 38. Example: Calculating CPI Typical Mix Base Machine (Reg / Reg) Op Freq Cycles CPI(i) (% Time) ALU 50% 1 .5 (33%) Load 20% 2 .4 (27%) Store 10% 2 .2 (13%) Branch 20% 2 .4 (27%) 1.5
  36. 39. Chapter Summary, #1 <ul><li>Designing to Last through Trends </li></ul><ul><ul><ul><ul><li>Capacity Speed </li></ul></ul></ul></ul><ul><li>Logic 2x in 3 years 2x in 3 years </li></ul><ul><li>DRAM 4x in 3 years 2x in 10 years </li></ul><ul><li>Disk 4x in 3 years 2x in 10 years </li></ul><ul><li>6yrs to graduate => 16X CPU speed, DRAM/Disk size </li></ul><ul><li>Time to run the task </li></ul><ul><ul><li>Execution time, response time, latency </li></ul></ul><ul><li>Tasks per day, hour, week, sec, ns, … </li></ul><ul><ul><li>Throughput, bandwidth </li></ul></ul><ul><li>“ X is n times faster than Y” means </li></ul><ul><li> ExTime(Y) Performance(X) </li></ul><ul><li> --------- = -------------- </li></ul><ul><li> ExTime(X) Performance(Y) </li></ul>
  37. 40. Chapter Summary, #2 <ul><li>Amdahl’s Law: </li></ul><ul><li>CPI Law: </li></ul><ul><li>Execution time is the REAL measure of computer performance! </li></ul><ul><li>Good products created when have: </li></ul><ul><ul><li>Good benchmarks, good ways to summarize performance </li></ul></ul><ul><li>Die Cost goes roughly with die area 4 </li></ul>Speedup overall = ExTime old ExTime new = 1 (1 - Fraction enhanced ) + Fraction enhanced Speedup enhanced CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle
  38. 41. Food for thought <ul><li>Two companies reports results on two benchmarks one on a Fortran benchmark suite and the other on a C++ benchmark suite. </li></ul><ul><li>Company A’s product outperforms Company B’s on the Fortran suite, the reverse holds true for the C++ suite. Assume the performance differences are similar in both cases. </li></ul><ul><li>Do you have enough information to compare the two products. What information will you need? </li></ul>
  39. 42. Food for Thought II <ul><li>In the CISC vs. RISC debate a key argument of the RISC movement was that because of its simplicity, RISC would always remain ahead. </li></ul><ul><li>If there were enough transistors to implement a CISC on chip, then those same transistors could implement a pipelined RISC </li></ul><ul><li>If there was enough to allow for a pipelined CISC there would be enough to have an on-chip cache for RISC. And so on. </li></ul><ul><li>After 20 years of this debate what do you think? </li></ul><ul><li>Hint: Think of commercial PC’s, Moore’s law and some of the data in the first chapter of the book (and on these slides) </li></ul>
  40. 43. Amdahl’s Law (answer) <ul><li>Floating point instructions improved to run 2X; but only 10% of actual instructions are FP </li></ul>Speedup overall = 1 0.95 = 1.053 ExTime new = ExTime old x (0.9 + .1/2) = 0.95 x ExTime old