3rd 3DDRESD: Rebit


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  • 3rd 3DDRESD: Rebit

    1. 1. Analysis and management of bitstream generators for Xilinx FPGAs Davide Candiloro: davide.candiloro@dresd.org Marco D. Santambrogio: marco.santambrogio@polimi.it P artial D ynamic R econfiguration W orkshop
    2. 2. Rationale <ul><li>Xilinx software is mainly tailored to static designs </li></ul><ul><li>Absence of validation or support for partial dynamic reconfiguration techniques </li></ul><ul><li>-therefore- </li></ul><ul><li>Development of a novel flow for the debugging and validation of partial dynamic reconfigurable architectures on Xilinx FPGAs </li></ul><ul><ul><li>Methodology to spot and address possible design flaws </li></ul></ul><ul><li>Design of a framework to automate and ease the designer’s task independently from vendor software </li></ul>
    3. 3. Detailed Contribution <ul><li>Automated constraint checking on Reconfigurable Regions </li></ul><ul><li>Guided error resolution and visual constraint editing </li></ul><ul><li>HW functionality area conflict monitoring </li></ul><ul><li>Exploration of the relocation possibilities for partial bitstreams </li></ul><ul><li>Analysis of the end result files of a PDR flow </li></ul><ul><li>Working on an architectural model and representation outside of Xilinx SW </li></ul>
    4. 4. Outline <ul><li>Partial dynamic reconfiguration and related issues </li></ul><ul><li>The proposed framework </li></ul><ul><li>Case study description </li></ul><ul><li>Case study application </li></ul><ul><li>Contributions </li></ul><ul><li>Future works </li></ul>
    5. 5. What’s next <ul><li>Partial dynamic reconfiguration and related issues </li></ul><ul><li>The proposed framework </li></ul><ul><li>Case study description </li></ul><ul><li>Case study application </li></ul><ul><li>Contributions </li></ul><ul><li>Future works </li></ul>
    6. 6. PDR flows and related issues <ul><li>The flows require the manual definition of RRs, conforming to specific guidelines </li></ul><ul><ul><li>The designer must refer correctly to the underlying architecture of the FPGA => error prone </li></ul></ul><ul><li>Vendor software has been designed for static designs </li></ul><ul><ul><li>There is no guarantee that the constraints for the RRs are respected by the Place and Route phase </li></ul></ul><ul><ul><li>This can inject further errors into the design: area conflicts and RR overflowing </li></ul></ul><ul><li>Designer efforts are taken away from the actual application development </li></ul>
    7. 7. PDR issue 1: RR definition <ul><li>The flows require constraints to be satisfied when defining RRs in the UCF ( User Constraints File ) file </li></ul>AREA_GROUP &quot;RR1&quot; RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP &quot;RR1&quot; RANGE = RAMB16_X2Y9:RAMB16_X2Y15;
    8. 8. PDR issue 2: Xilinx PAR programs <ul><li>Place and Route built for static designs </li></ul><ul><li>Even if RR defined correctly, HW might overflow it </li></ul><ul><li>This situation is NOT reported to the designer </li></ul><ul><li>Can inject silent errors in the design due to configuration overwriting and area conflicts </li></ul>
    9. 9. State of the art <ul><li>Planahead ® - 2008 </li></ul><ul><ul><li>Used to constrain the logic inside particular regions </li></ul></ul><ul><ul><li>Last version adds PDR support </li></ul></ul><ul><ul><li>An error situation is simply reported but </li></ul></ul><ul><ul><ul><li>- not where - not how to overcome it </li></ul></ul></ul><ul><li>Floorplanner ® - 2008 </li></ul><ul><ul><li>Editor for the constraints of regions on the chip </li></ul></ul><ul><ul><li>Architecture-aware </li></ul></ul><ul><ul><li>NOT reconfiguration aware => guidelines not enforced </li></ul></ul><ul><li>Chipscope ® - 2008 </li></ul><ul><ul><li>Used in debugging designs on Xilinx FPGAs </li></ul></ul><ul><ul><li>Only AFTER the design has been downloaded on board </li></ul></ul><ul><li>Jbits ( discontinued ) - 2004/5 </li></ul><ul><ul><li>Provided low level access to configuration in bitstreams </li></ul></ul>
    10. 10. What’s next <ul><li>Partial dynamic reconfiguration and related issues </li></ul><ul><li>The proposed framework </li></ul><ul><li>Case study description </li></ul><ul><li>Case study application </li></ul><ul><li>Contributions </li></ul><ul><li>Future works </li></ul>
    11. 11. Integration with the Earendil flow <ul><li>Existing flow for defining FPGA reconfigurable apps </li></ul><ul><li>Proposed flow at the end of Earendil chain </li></ul><ul><li>Based upon reconfigurable architecture product files </li></ul><ul><li>May thus be inserted at the end of generic flows </li></ul>
    12. 12. Rebit: the proposed framework C++ wxWidgets
    13. 13. Conflict Graph Conflict graph conflict=edge Incidence Matrix conflict=red which functionalities can be used at the same time?
    14. 14. Demo description <ul><li>Application </li></ul><ul><ul><li>Edge detection on black and white digital images </li></ul></ul><ul><ul><ul><li>Input: color digital images </li></ul></ul></ul><ul><ul><ul><li>Output: edge detected on the input images </li></ul></ul></ul><ul><li>Architecture </li></ul><ul><ul><li>2 IP-Cores </li></ul></ul><ul><ul><ul><li>Filter (gray scale converter) </li></ul></ul></ul><ul><ul><ul><li>Edge Detector (E.D.) </li></ul></ul></ul><ul><ul><li>Static area </li></ul></ul><ul><ul><ul><li>GPP: PPC405 </li></ul></ul></ul><ul><ul><ul><li>SW: standalone </li></ul></ul></ul><ul><ul><li>Reconfigurable area </li></ul></ul><ul><ul><ul><li>1 reconfigurable regions </li></ul></ul></ul>
    15. 15. Data flow <ul><li>sddd </li></ul>Input image Gray scale (Filter) Edge Detection (E.D.)
    16. 16. Performance analysis (1)
    17. 17. Reconfiguration performance <ul><li>Area (Xilinx VIIP7) </li></ul><ul><ul><li>System </li></ul></ul><ul><ul><ul><li>Static area </li></ul></ul></ul><ul><ul><ul><ul><li>Slices: 2100 </li></ul></ul></ul></ul><ul><ul><ul><li>Reconfigurable area </li></ul></ul></ul><ul><ul><ul><ul><li>Constrained slices : 896 </li></ul></ul></ul></ul><ul><ul><li>RFUs </li></ul></ul><ul><ul><ul><li>Filter (Gray scale) </li></ul></ul></ul><ul><ul><ul><ul><li># Frames: 126 </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Bitstream size: 110 KB </li></ul></ul></ul></ul><ul><ul><ul><li>Edge Detector (E.D.) </li></ul></ul></ul><ul><ul><ul><ul><li># Frames: 158 </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Bitstream size: 110 KB </li></ul></ul></ul></ul><ul><li>Reconfiguration performance </li></ul><ul><ul><li>Execution time: 0.31s </li></ul></ul><ul><ul><li>Rec. troughput :1,02 MB/sec </li></ul></ul><ul><ul><li>Rec. time: 0,1 sec </li></ul></ul><ul><ul><li>min data size: 32353 byte </li></ul></ul><ul><ul><ul><li>min image size: 180x180 </li></ul></ul></ul>
    18. 18. Performance analysis
    19. 19. Enhancement exploration <ul><li>Is there any way in which we can enhance the application performance/flexibility? </li></ul><ul><li>Yes! </li></ul><ul><li>Exploring new design solutions using REBIT </li></ul><ul><li>(we will now see how) </li></ul>
    20. 20. Performance analysis
    21. 21. Case study: architecture <ul><li>2 image filters </li></ul><ul><li>2 partial bitstrams </li></ul><ul><li>1 RR </li></ul><ul><li>Synthesis finished, we now aim at: </li></ul><ul><ul><li>Finding flaws in the design, if any </li></ul></ul><ul><ul><li>Correcting them </li></ul></ul>
    22. 22. Case study: constraint validation
    23. 23. Case study: UCF editing
    24. 24. Case study: relocation <ul><li>We have resolved the issues of the design… </li></ul><ul><li>Now we would like to explore new solutions </li></ul>
    25. 25. Case study: area conflicts
    26. 26. What’s next <ul><li>Partial dynamic reconfiguration and related issues </li></ul><ul><li>The proposed framework </li></ul><ul><li>Case study description </li></ul><ul><li>Case study application </li></ul><ul><li>Contributions </li></ul><ul><li>Future works </li></ul>
    27. 27. Contributions of the work <ul><li>Novel flow for the DRC of PDR architectures </li></ul><ul><li>Automation of the flow for the validation and debug of PDR architectures: no more manual steps </li></ul><ul><li>Visual editing and guided issue resolution </li></ul><ul><li>Configuration memory maps for the analyzed FPGAs </li></ul><ul><li>Relation of Xilinx bitstream format to the specific architecture </li></ul><ul><li>Development of a framework independent of Xilinx software that integrates knowledge of the architectural details </li></ul>
    28. 28. Future works <ul><li>Adding support for new/other FPGAs to the system </li></ul><ul><li>Turn the reasoner module into an expert system , to develop further automation in the definition and validation of the system </li></ul><ul><li>Taking BUS Macros into account, i.e.: communication between different RFUs </li></ul><ul><li>Extend the data model with board data , not only chip </li></ul><ul><ul><li>Develop methodologies to generate constraints based on IOB connections to the external board components </li></ul></ul>
    29. 29. Questions