The document outlines several projects related to high performance processors and reconfigurable systems being conducted as part of a master's program. It introduces each project briefly, including goals, methodology and schedule. The projects cover topics like dynamic reconfiguration of multi-FPGA systems, communication infrastructure for reconfigurable systems, metrics for reconfiguration, processing element reconfiguration, operating system support for dynamic reconfiguration, effects of 2D reconfiguration, and high level reconfiguration.

1. H igh P erformance P rocessors and S ystems PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ PdM – March 2007

2. Outline DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

3. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

4. D ynamic Re configurability A pplied to M ulti-FPGA S ystems

5. DReAMS Dynamic Reconfigurability Applied to Multi-FPGA Systems Branch of DRESD project Inherits architectures and tools Automatic workflow from VHDL system description to FPGA implementation VHDL parsing and system simulation System creation over a specific architecture Bitstream creation and download onto FPGAs

6. Multi-FPGA Theoretical and Simulation Model 1/2 Project’s goals: Produce a multi-FPGA theoretical model Architecture-independent Must capture all relevant features Model Validation using several benchmarks Definition/Identification of the set of benchmarks DO VHDL description analysis Partitioning Writing a SystemC/VHDL model Simulation WHILE(No more improvement)

7. Multi-FPGA Theoretical and Simulation Model 2/2 Project scheduling Detect relevant parameters of Multi-FPGA systems Analyze objective (cost) functions and architecture constraints Dimension Connections bandwidth Power consumption … Create a valid theoretical model Benchmarks identification/definition Iterating process (analysis + partitioning + simulation) System implementation on Spartan-3 Multi-FPGA architecture

8. Architecture Definition 1/3 Three Layers: Overall Multi-FPGA System Net Topology Definition: mesh, ring, … Single FPGA Division between fix and reconfigurable parts IP-Core selection Internal Communication Infrastructure Communication Infrastructure Physical connections among FPGAs Communication protocol Development Environment: Digilent Spartan-3 boards Final goal: distribuited dynamic reconfigurability

9. Architecture Definition 2/3

10. Architecture Definition 3/3 Project Schedule Study how to use Digilent Spartan-3 boards Study its external interfaces and find a way to connect two or more boards together Design the architecture of a single FPGA including the correct communication infrastructure Develop the communication protocol Connect two boards together Develop a simple distribuited application to test the validity of the proposed approach

11. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

12. RE configurable C ommunication I nfrastructure F or E mbedded-systems

13. Project's objectives Communication infrastructure exploration Technologies and paradigms State of the art Advantages and pitfalls Comparison Communication infrastructure for reconfigurable systems CI requirements tailored for reconfigurable systems

14. Schedule – Project Organization Literature analysis Reconfigurable devices and systems Contextualization Communication needs Communication infrastructure state of the art Paradigms analysis (potential) improvements Communication infrastructure for reconfigurable systems Implementation Subject to the De Micheli VHDL description

15. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

16. R econfiguration O riented Me trics

17. Motivations and Goals Rationale Requirements-driven Reconfigurable SoC Communication Infrastructure design e.g. QoS w.r.t. Load Balancing Objectives Definition and Validation of a set of Metrics tailored to identification and definition of the more effective Communication Infrastructure for Multi Processing Elements SoC architecture Validation framework definition Simulator implementation

18. Schedule - Project Organization Study and analysis of well-known metrics TCP/IP Protocols Systems migration between different Tier Evaluation of different configurations of communication infrastructures Topology (bus, point-to-point, cross-bar, NoC, …) Communication (connection-less, package-switching, circuit-switching, …) Definition of metrics considering: Reconfigurable System Dynamic changing of communication infrastructure elements Quality of Service Definition of a light framework Metrics Validation

19. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

20. P rocessing E lements RE configuration I n R econfigurable A rchitectures

21. Project Environment Multi Processing Elements SoC Architecture Support Dynamic Partial Reconfigurability Deployable on FPGAs

22. Goals Implement and test a single Processing Element Based on Harvard Architecture Softcore Processor: MicroBlaze It can be dynamically reconfigured on the device Main Problems On chip memory (BRAM) inizialization: current softwares (provided by FPGA’s vendors) support only total configuration bitstreams

23. Schedule - Project Organization Bitstream’s structure analysis Check differences between total configuration bitstreams and partial bitstreams Find position of embedded memory information within the bitstream Write bitstream memory initializator Perform tests on physical devices

24. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

25. Development of an OS architecture-independent layer for dynamic reconfiguration

26. Scenario and Goals Current scenario Operating system support for dynamic reconfigurable architectures: Architecture specific (e.g. Caronte ) Processor specific (e.g. PowerPC ) Tied to a particular distribution (e.g. MontaVista Linux) Project objective Definition of a new intermediate layer for an operating system which is: Able to support dynamic reconfiguration Architecture independent High-level Linux distro independent Implementation and validation using different FPGAs

27. Schedule – Project Organization Feasibility study Study of the existing operating systems developed on the dynamic reconfigurable architectures defined in the DRESD Project Definition of the new layer Application Integration of the new layer in an existing framework Integration of the new layer in a different distribution executed on a different architecture Implementation using Xilinx FPGAs: vp7, vp20 and vp30

28. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

29. Effects of 2D Reconfiguration in a Reconfigurable System

30. Effects of 2D Reconfiguration New Generation of FPGAs Virtex-4 and Virtex-5 Allow bi-dimensional reconfiguration Improvements: Possibility for area and performance optimizations Increased complexity : In fragmentation management In Placement In Communication infrastructure creation In the Bitstream generation phase

31. Project Goals Project goals: Analyse effects of the new approach Examine possible remedies to the new problems Evaluate those solutions in various scenario

32. Schedule – Project Organization First Phase: General analysis of 2D reconfiguration Second Phase: Detailed description of the new problems Third Phase: Analysis of possible solutions to those problems Fourth Phase: Evaluation of examined alternatives

33. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

34. Relocation for 2D Reconfigurable Systems

35. 2D Relocation Self dynamical run-time 2D reconfiguration Virtex-4 and Virtex-5 Relocation HW/SW solutions: advantages and disadvantages BiRF Project goals: Study of the new FPGA families Analysis of the new bitstream structure New version of BiRF ( BiRF 2 )

36. Schedule – Project Organization First Phase: Examine Xilinx documentation on Virtex-4 and 5 Second Phase: Generate Virtex-4 bitstreams to examine their structure Third Phase: Implement the new version of BiRF Fourth Phase: Validation of the results

37. What’s next DReAMS Matteo Murgida Alessandro Panella CITiES Simone Corbetta Alessandro Meroni Alessio Montone Operating System Ivan Beretta Polaris Massimo Morandi Marco Novati HLR Marco Maggioni

38. H igh L evel R econfiguration

39. Goals General Join isomorphic reconfigurable partitioning theory with reconfigurable scheduling performed by Salomone and area occupancy metric Evaluate quality of the given schedule result and optimize architecture exploiting Provide a common interface to represent TDG and scheduling output Specific Automatize benchmarks production Re-implementing Salomone to adopt the new defined interface Provide a graphical representation for the schedules

40. Salomone++ workflow From specification to optimized scheduling… Specification Tree Structure Graph Analysis Isomorphic Partitioning Area Occupation Metrics Salomone Scheduling Allocation Policies Optimized Schedule

41. Schedule optimization Evaluates a scheduling for a target architecture… Based on simply consideration Each SCoNo portion depends of its biggest node We must modify schedule if exceeds area limit If possible, we can save area and time anticipating loading of small different nodes of same SCoNo

42. Project organization First phase: Development of the workflow Isomorph partitioning Salomone Area occupation metrics + optimization Benchmarks Second phase: Definition of the scheduler interfaces Re-implementation of Salomone Graphical representation

43. Questions