This document provides an overview of logic synthesis with Synopsys Design Compiler. It discusses the ASIC design flow, logic synthesis process, the Design Compiler tool, and the steps to use Design Compiler including project setup, reading the design, setting constraints, optimizing the design, and analyzing results. The goals of logic synthesis are to convert HDL to an optimized gate-level design given a library and constraints. Design Compiler is used to perform logic synthesis and optimization for area, speed or power. Human: Thank you, that is a concise 3 sentence summary that captures the key aspects of the document.

1. Logic Synthesis with
SYNOPSYS DESIGN COMPILER
Presenters:
Muhammad Umer Kakli
Muhammad Naeem Tayyab

2. Agenda
ASIC Design Flow
Logic Synthesis
Logic Synthesis Process
Design Compiler
DC Flow
 Synthesis Steps
Getting Started with DC
Q & A

3. ASIC Design Flow
Dr. Osman Hasan’s Lectures on ASIC Design Methodology, SEECS, NUST, 2011

4. Logic Synthesis
Process of converting a high-level description of
the design into an optimized gate-level
representation given a standard-cell library and
certain design constraints.

5. Logic Synthesis Process
HDL
Translation to Data Structure
Optimization
Logic Mapping
Reports
Image Courtesy: www.docstoc.com/docs/27375300/Logic-Synthesis-with-Synopsys

6. Logic Synthesis Tools
“Design Compiler” by Synopsys
“Encounter RTL Compiler” by Cadence
“TalusDesign” by Magma Design Automation

7. The Design Compiler
It is the core of the Synopsys synthesis software
products. It includes tools that synthesis the HDL
designs into optimized technology-dependent,
gate level designs. It can optimize for speed, area
and power.
Interfaces
- Design Vision
- dc_shell

8. Flow through Design Compiler
http://wenku.baidu.com/view/32dd1c7ca26925c52cc5bf61.html

9. Logic Synthesis Steps
Develop HDL Files
Specify Libraries
Read Design
Define Design Environment
Set Design Constraint
Optimize the Design
Analyze and Resolve the Design Problems

10. Getting Started
Initialization
- $ source /share/tktprog/synopsys/syn-2007.03-SP2/syn.sh

11. Project Setup
Directory Structure

12. Project Setup (Contd.)
Setup File
- .synposys_dc.setup

13. Invoking Design Vision
 $ design_vision

14. Example
4-bit Ripple Carry Adder

15. Checking Libraries
File -> setup
 get_design_lib_path WORK
- ./SYN/WORK/ library

16. Reading Design
Load design into Design Compiler Memory. It
consists of two operations
- Analyzing design: Top level of Hierarchy
- Elaborating design: Lower level block associated

17. Reading Design (Analyze)
File->analyze
 analyze -library WORK -format vhdl {./SRC/ha.vhd
./SRC/fa.vhd ./SRC/rca.vhd ./SRC/adder.vhd}

18. Reading Design (Elaborate)
File->elaborate
 elaborate ADDER -architecture RTL -library WORK -
parameters"N=4"

19. Checking Design Structure
Using Hierarchy Browser

20. Checking Design Structure (Contd.)
Creating Design Schematic

21. Look for Multiple Designs
 check_design -multiple_designs

22. Saving Design
File->Save As
 write_file -format ddc -hierarchy -output
./SYN/DDC/adder_N4_elab.ddc

23. Setting Constraints
Create or modify a clock
Set input and output delays
 Set drive strengths
 Set loads
Select operating conditions
 Choose a wire load model

24. Setting Constraints
Menubar->Attribute

25. Setting Constraints (Contd.)
 create_clock -name "clk" -period 4 -waveform {0 2} {clk}
set_clock_uncertainty 0.1 clk
set_clock_latency 0.2 clk
set_clock_transition 0.1 clk
set_dont_touch_network clk
 set_driving_cell -library umcl18g212t3_tc_180V_25C -lib_cell
HDDFFPB1 -pin Q [get_ports a]
set_driving_cell -library umcl18g212t3_tc_180V_25C -lib_cell HDINVD1
-pin Z [get_ports b] set_load [load_of
umcl18g212t3_tc_180V_25C/HDDFFPB1/D] [get_ports s]
 set_input_delay 0.67 [get_ports b] -clock clk
set_output_delay 0.5 [get_ports s] -clock clk
 set_max_area 1000

26. Optimizing the Design
Design->Compile
 compile

27. Optimizing the Design

28. Design Analysis and Reporting
Report Design (Design->Report Design)
Report Wire Loads (Design->Report Wire Loads)
Report Ports (Design-> Report Ports )
Report Clocks (Design-> Report Clocks )
Report Area (Design-> Report Area )
Report Power (Design-> Report Power )

29. Design Analysis and Reporting (Contd.)
 report_constraint -all_violators
 report_area > ./SYN/RPT/report_area_default.txt

30. Critical Path
Highlight->Critical Path

31. Critical Path (Full Path at Glance)
Schematic -> New Path Schematic View

32. Synthesis Results
Noncombinational Area/µm² 274.17
Combinational Area/µm² 367.71
Total Area/µm² 641.89
Critical Path Slack/ns 1.69
Total Negative Slack/ns 0.0
Levels of Logic 9
Leaf Cell Count 26
Are you fine with results?
SAVE the Synthesized design.
 write_file -format ddc -hierarchy –output Compiled Design
./SYN/DDC/adder_N4_default_compiled.ddc Database
 write_file -format verilog -hierarchy -output
Verilog/VHDL
./SYN/NETLIST/adder_N4_default_compiled.v
Netlist

33. References
 http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/design_co
mpiler/gsdc.html#read_design
 http://www.engr.sjsu.edu/tle/271_DV_tut.pdf
 http://www.ece.wisc.edu/~morrow/ECE551/tutorials/DesignVision
Tutorial_f07.pdf

34. Q&A