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RCIM 2008 - - hArtes_Ferrara


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RCIM 2008 - - hArtes_Ferrara

  1. 1. The hardware application platform of the hArtes project Università degli Studi di Ferrara - Dipartimento di Fisica RCIM - Milano – December 19th, 2008
  2. 2. <ul><li>hArtes’ main goal: support, with appropriate tools, the development of complex applications on embedded heterogeneous reconfigurable systems. Our hardware platform provides a number of heterogeneous computing sub-systems, such as DSPs, general-purpose CPUs and configurable elements (in the shape of FPGAs). Demonstrators for the applications: mainly in the audio realm  support for high-quality I/O audio subsystems on the platform. </li></ul><ul><li>Roles of the FPGAs in the platform architecture: </li></ul><ul><li>one FPGA-based subsystem supports the complex I/O system for audio streams, moving audio signals from/to platform shared memory with full hardware support; </li></ul><ul><li>two high-end FPGAs, tightly coupled to traditional processors, make up the reconfigurable core of the processor, whose exploitation will be made possible to designers without specific FPGA know-how by the hArtes software tools. </li></ul>The hardware application platform of the hArtes project
  3. 3. <ul><li>Demonstrator applications are currently focused on two fields: </li></ul><ul><li>audio applications for advanced Car Information Systems (CIS) </li></ul><ul><li>immersive audio (e.g., Teleconferencing). </li></ul><ul><li>These fields require different levels of complexity: computational load ranging from 2 to more than 10 Gflops; I/O requirements ranging from few low-quality audio channels up to 64/32 high-quality, digital audio channels (24 bits per sample at 48/96 KHz sampling rate). </li></ul><ul><li>Key features required by the applications : </li></ul><ul><li>(1) integrate several elements of an heterogeneous computer architecture and provide sufficient interconnection between them to support tightly-coupled computational tasks; </li></ul><ul><li>(2) support a modular system structure, starting from a simple and cheap entry-level configuration and extending to more performing systems (up to a computational power of some tens of Gflops); </li></ul><ul><li>(3) an architecture in which new processing elements (that is, additional heterogeneous components) can be incorporated in a compatible way at a later stage of the design process; </li></ul><ul><li>(4) provide adequate I/O channels, both general purpose (e.g., USB, Ethernet) and with specific standards applicable for audio signal processing (e.g., ADAT lightpipe). </li></ul>Application requirements
  4. 4. Main Board architecture hArtes hardware platform overview
  5. 5. Xilinx XC4VFX100
  6. 6. Main board with all daughter boards BACK FRONT
  7. 7. Main board layout BACK FRONT
  8. 8. (320) Floorplan of the XC4VFX100 device (320, not used ) (128) Fixed function IPs area Re-programmable area Internal organization of the BCE FPGA
  9. 9. Actual internal organization Re-programmable area Fixed function IPs area
  10. 10. (Preliminary) MOLEN architecture support in the BCE For a description of the MOLEN architecture, please visit the TU-Delft CE website:
  11. 11. The plaftorm @ work: the audio demo developed for the 2nd hArtes review
  12. 12. The plaftorm @ work: the audio demo developed for the 2nd hArtes review MOTU ADAT interface PC optical fibres
  13. 13. The plaftorm @ work: the audio demo developed for the 2nd hArtes review audio streaming support (64 audio channels in + 64 out)
  14. 14. The plaftorm @ work: the audio demo developed for the 2nd hArtes review audio streaming support (64 audio channels in + 64 out) Audio streaming (input push, output pull) Audio buffering Interrupts for all 64+64 channels Fully performed at hard(firm)-ware level Soft-configurable
  15. 15. Conclusions <ul><li>We developed an hardware platform to suit the requirements of the toolchain and demonstrator applications for the hArtes project. </li></ul><ul><li>The hardware platform is currently ready for the integration with the toolchain and with the MOLEN architecture. </li></ul><ul><li>In the future we plan to develop an improved version of the platform, using feedbacks provided by the experience of the first application tests; performance improvements are also foreseen, as we plan to deploy four BCEs on a new system (depending of applications requirements). Acknowledgments </li></ul><ul><li>This work is sponsored by the hArtes project (IST-035143), supported by the Sixth Framework Programme of the European Community under the thematic area ”Embedded Systems”. </li></ul>