1. VHDL: una breve introduzione DRESD H ow T o (DHow2) – L1 DRESD Team [email_address]
2.
3. Introduzione Il Linguaggio VHDL viene utilizzato per: Documentare, Simulare, Sintetizzare circuiti e sistemi logici. Esso è costituito da più parti alcune delle quali fanno parte integrale del linguaggio stesso, mentre altre vengono integrate da opportuni “packages” realizzati all’interno di “libraries”
22. Ripple Carry Adder Ripple-Carry Architecture Full Adder x 0 y 0 c 0 s 0 Full Adder x 1 y 1 c 1 c 2 s 1 Full Adder x n-1 y n-1 c n-1 c n s n-1 n-bit Ripple Carry Adder s n-1 s 0 x n-1 y n-1 x 0 y 0 c 0 c n Ripple-Carry Adder
23. n-bit Ripple Carry Adder s n-1 s 0 x n-1 y n-1 x 0 y 0 n-bit Ripple Carry Adder s 2n-1 s n x 2n-1 y 2n-1 x n y n x kn-1 y kn-1 c 0 c n c 2n Ripple Carry Block Adder n-bit Ripple Carry Adder s kn-1 s (k-1)n c (k-1)n c kn
24.
25.
26. Carry Look-Ahead Adder Carry Look-Ahead Logic: Internal architecture CLA Logic c 0 c n x 0 y 0 x n-1 y n-1 c n-1 c 1 Carry Look-Ahead Logic x 0 y 0 G 0 P 0 c 0 c 1 x 1 y 1 G 1 P 1 c 2 G n-1 P n-1 x n-1 y n-1
27.
28. Carry Look-Ahead Adder Carry Look-Ahead Logic Carry Look-Ahead Logic Full Adder c 0 s 0 Full Adder c 1 s 1 Full Adder x n-1 y n-1 s n-1 c n-1 x 1 y 1 x 0 y 0 c n x 0 y 0 x n-1 y n-1
34. HA: Descrizione comportamentale ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS; END half_adder_a;
35. HA: Descrizione dataflow ARCHITECTURE half_adder_b OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_b;
36.
37. HA: Descrizione strutturale -- continuing half_adder_c description SIGNAL xor_res : BIT; -- internal signal -- Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_c;
![VHDL: una breve introduzione DRESD H ow T o (DHow2) – L1 DRESD Team [email_address]](https://image.slidesharecdn.com/l1-1227868839593501-9/85/DHow2-L1-1-320.jpg)
![VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)