3D-DRESD DReAMS

DReAMS Dynamic Reconfigurability Applied to Multi-FPGA Systems Matteo Murgida, Alessandro Panella {matteo.murgida, alessandro.panella}@dresd.org

DReAMS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

SPartA A novel algorithm for multi-FPGA partitioning Alessandro Panella [email_address]

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Problem description ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Project goals and contributions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

What is partitioning? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Existing approaches - a glance ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Going deeper into the problem ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

SPartA: the framework ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

SPartA: the idea ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],(*) (*) From Wen-Jong Fang and Allen C.-H. Wu, Multiway FPGA Partitioning by Fully Exploiting Design Hierarchy

SPartA: the algorithm 1/2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

SPartA: the algorithm 2/2 ,[object Object],[object Object],[object Object],[object Object]

Results 1/3 ,[object Object],[object Object],[object Object],ORIGINAL TREE PARTITIONED TREE

Results 2/3 ,[object Object],[object Object],[object Object],[object Object]

Future work ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Chimera Multi-FPGAs Architecture Definition Matteo Murgida [email_address]

Murgida - Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Problem Description ,[object Object],[object Object]

Project Goals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

State of the Art ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Contributions ,[object Object],[object Object],[object Object],[object Object]

Board Study ,[object Object],[object Object],[object Object]

Microblaze Communication ,[object Object],[object Object]

GPIO Insertion ,[object Object]

Interrupt Controller Insertion ,[object Object],[object Object]

Timeout ,[object Object],[object Object],[object Object],[object Object]

Future Works ,[object Object],[object Object]

3D-DRESD DReAMS

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3D-DRESD DReAMS