The SPI (Serial Peripheral Interface) is a synchronous serial communication protocol used for communication between devices. It uses a master-slave architecture with a single master device initiating data transfer. Key features include using separate clock and data lines, operating in full duplex mode, and allowing multiple slave devices through individual chip selects. It provides a lower pin count solution than parallel buses at the cost of slower communication speeds.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
The document discusses the Inter-Integrated Circuit (I2C) protocol. It was developed by Philips in the 1980s as a simpler way to connect peripherals in devices like TVs that previously used separate wiring for each component. I2C uses just two bidirectional lines (SCL for clock and SDA for data) and allows for multiple master and slave devices to communicate at speeds up to 3.4 Mbps using 7- or 10-bit addressing. Devices operate on a master-slave model where the master controls the bus by generating the clock signal and addressing slave devices to send or receive data.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
The Advanced Microcontroller Bus Architecture (AMBA) specification defines interfaces for connecting processor and peripherals. It aims to standardize connections to enable modular system design. The Advanced Peripheral Bus (APB) is defined by AMBA for simple peripherals like timers and I/O. It uses few signals for non-pipelined transfers in two cycles to reduce power and complexity.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
The document discusses the Inter-Integrated Circuit (I2C) protocol. It was developed by Philips in the 1980s as a simpler way to connect peripherals in devices like TVs that previously used separate wiring for each component. I2C uses just two bidirectional lines (SCL for clock and SDA for data) and allows for multiple master and slave devices to communicate at speeds up to 3.4 Mbps using 7- or 10-bit addressing. Devices operate on a master-slave model where the master controls the bus by generating the clock signal and addressing slave devices to send or receive data.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
The Advanced Microcontroller Bus Architecture (AMBA) specification defines interfaces for connecting processor and peripherals. It aims to standardize connections to enable modular system design. The Advanced Peripheral Bus (APB) is defined by AMBA for simple peripherals like timers and I/O. It uses few signals for non-pipelined transfers in two cycles to reduce power and complexity.
PCIe is a standard expansion card interface introduced in 2004 to replace PCI and PCI-X. It uses serial instead of parallel communication and is scalable, allowing for higher maximum system bandwidth. The presentation discusses the history of expansion card standards leading to PCIe, including ISA, EISA, VESA, PCI, and PCI-X. It also covers key aspects of PCIe such as the root complex, endpoints, switches, lanes, bus:device.function notation, enumeration, and address spaces such as configuration space.
This document provides an overview of the I2C communication protocol. It describes that I2C is a serial communication protocol used to connect slow devices like EEPROMs and ADCs. It can operate at speeds from 100 kbps to 5 Mbps and supports both single master-multi slave and multi master-multi slave configurations. The document outlines the electrical characteristics, bus features, data frame structure, data transfer process, clock synchronization, arbitration and advantages of the I2C protocol.
The document describes the AMBA 3 APB protocol. It has an unpipelined design to reduce complexity and power consumption. Transfers take at least two cycles with the first being a setup phase and second an access phase controlled by the PENABLE signal. Slaves can extend transfers using the PREADY signal. Errors are indicated by PSLVERR. The protocol defines read and write transfers with or without wait states.
The document describes conventions and signals used in the AMBA 3 APB protocol specification version 1.0. It summarizes write and read transfer procedures, including optional wait states using the PREADY signal. Error responses are also described. The operating states of the APB include IDLE, SETUP, and ACCESS states. PREADY controls exiting the ACCESS state.
The AXI protocol specification describes an advanced bus architecture with burst-based transactions using separate address/control and data phases over independent channels. It supports features like out-of-order transaction completion, exclusive access for atomic operations, cache coherency, and a low power interface. The AXI protocol is commonly used in System-on-Chip designs for high performance embedded processors and peripherals.
Dual-ported RAM allows reads and writes from multiple sources simultaneously, unlike single-ported RAM which allows only one access at a time. It increases bandwidth and reduces design complexity compared to alternatives. Dual-ported RAM is commonly used to enable independent communication between two processors, such as in set-top boxes to transmit and store digital television programs between a CPU and peripheral components.
The document discusses the I2C communication bus protocol. It describes the I2C bus concept of using two bi-directional lines (SDA and SCL) to allow devices with unique addresses to communicate as masters or slaves. The document outlines the I2C communication protocol including START/STOP conditions, byte format, acknowledgment, synchronization, arbitration, and 7-bit and 10-bit addressing schemes. Key aspects of the I2C bus such as typical transfer rates, hardware connections, and terminology are also summarized.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) communication. It describes how UARTs allow for asynchronous serial communication between devices using only 2 wires by converting parallel data to serial and vice versa. The UART communication process involves a transmitting UART adding start, stop and optionally parity bits to data before transmitting it serially bit-by-bit to a receiving UART which reconstructs the parallel data. It also discusses the TTL and RS-232 physical layer standards for UART.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
The document discusses various methods for automatic test pattern generation (ATPG) in testing VLSI circuits, including:
1) Exhaustive and pseudo-exhaustive methods that test all possible patterns but are infeasible for large circuits.
2) Random and weighted random methods that provide confidence in detecting faults but quality depends on the circuit.
3) Deterministic methods like Boolean difference that compute test vectors to detect specific faults more efficiently than examining all vectors.
4) ATPG uses a two-phase approach - random pattern generation and fault simulation initially to detect many faults easily, followed by targeted deterministic pattern generation to detect remaining faults.
its only for learning purpose for beginners who wants to understand this protocol.
Life is all about learning, hope u will enjoy in this my PPT.
for any suggestion your always welcome .
This document provides an overview of the I2C protocol. It describes that I2C was designed by Philips in the 1980s to allow communication between components on the same circuit board. It has since been migrated to NXP and expanded to support higher bus speeds and lower voltages. The document outlines the I2C architecture as a half-duplex, synchronous, multi-master bus using a serial data line and serial clock. It defines I2C nodes can function as a master or slave and transmit or receive data. Electrical characteristics, start/stop conditions, packet formats, clock stretching, arbitration and multi-byte transactions are also summarized.
MIPI DevCon 2016: A Developer's Guide to MIPI I3C ImplementationMIPI Alliance
In this presentation, Intel's Ken Foust, MIPI Sensor Working Group Chair, provides early adopters of MIPI I3C with targeted guidance on how to ensure a successful and efficient implementation of MIPI I3C in their products.
Leveraging I2C as a foundation, many components of MIPI I3C will be familiar to implementers, but with guidance provided here, viewers will gain a clearer understanding of MIPI I3C’s new innovative features, how they will improve their systems, and what considerations should be made to fully leverage them.
The document describes the I2C (Inter-Integrated Circuit) bus interface. I2C is a digital communication protocol used to connect integrated circuits on the same circuit board. It uses just two bidirectional open-drain lines - serial data (SDA) and serial clock (SCL). Devices on the I2C bus can operate as either a master or slave. The master device initiates and controls data transfers. Slave devices respond to the master's commands. The document outlines the electrical considerations, addressing schemes, data transfer protocols, and how to implement I2C on a PIC18F25K22 microcontroller.
The document discusses various ATPG (Automatic Test Pattern Generation) methods and algorithms. It provides an introduction to ATPG, explaining that ATPG generates test patterns to detect faults in circuits. It then covers major ATPG classifications like pseudorandom, ad-hoc, and algorithmic. Several algorithmic ATPG methods are described, including the D-algorithm, PODEM, FAN, and genetic algorithms. Sequential ATPG is more complex due to memory elements. The summary reiterates that testing large circuits is difficult and many ATPG methods have been developed for combinational and sequential circuits.
The PIC microcontroller uses a Harvard architecture with separate program and data memories. It has a CPU with an ALU, memory unit, and control unit. The memory includes program memory to store instructions, data memory including registers for temporary data storage, and EEPROM for storing variables. It has advantages like a small instruction set, low cost, and built-in interfaces like I2C, SPI, and analog components.
The document describes the Serial Peripheral Interface (SPI) protocol which allows for full duplex synchronous serial communication between a master and slave device using 4 pins - MOSI, MISO, SCK, and an optional SS pin. It details the SPI registers for control, status, and data and provides examples of SPI communication with peripherals like digital pots and shift registers. Common issues like conflicts with programming interfaces and ensuring proper chip select signaling are also covered.
Microcontrollers are small computers that integrate RAM, ROM, I/O ports and other components onto a single chip. They are used in applications where cost, power and space are critical. The document compares microprocessors and microcontrollers, noting that microcontrollers have all components on one chip while microprocessors have separate chips. It then describes the typical internal blocks of a microcontroller, including the CPU, memory, I/O ports, timers and serial ports. Block diagrams show the connections between these internal components.
I2c protocol - Inter–Integrated Circuit Communication ProtocolAnkur Soni
This document provides an overview of the I2C communication protocol. It describes how I2C uses only two wires (SDA and SCL) to allow data transmission between an I2C master and multiple I2C slave devices. The document explains the I2C message structure, including the start condition, address frame, read/write bit, data frames, ACK/NACK bits, and stop condition. It also discusses the advantages of I2C, such as supporting multiple masters/slaves and error checking, and disadvantages like slower speeds compared to SPI. Real-life uses of I2C include connections to OLED displays, sensors, and other peripherals.
I2C is a serial communication protocol used to connect low-speed peripherals to processors and microcontrollers. It was developed by Philips in the 1980s for use in televisions. I2C uses just two bidirectional open-drain lines: serial data line (SDA) and serial clock line (SCL). Devices can operate as master or slave devices and have a 7-bit address. Communication is initiated by the master which controls the clock signal. Data is transferred in one byte packets with acknowledgement from the receiver.
Serial Peripheral Interface (SPI) is a communication protocol developed by Motorola for serial communication. It uses a master-slave architecture with 4 connection wires - MOSI, MISO, SCLK, and SS. The master device controls the clock signal and initiates data transfer to and from the slave devices. SPI allows for full duplex communication at high speeds and is commonly used with peripherals like converters, memories, sensors, and displays. While it provides high throughput, SPI requires more pins than alternatives like I2C and does not have hardware flow control or slave acknowledgement.
The document describes the verification of an SPI master core using UVM. It provides details on the SPI protocol, the master core architecture and features, testbench components like agents and scoreboard, testcases that were run, and two bugs that were discovered. The verification covered functionality like different data transfer configurations and achieved 92.85% coverage of the design.
PCIe is a standard expansion card interface introduced in 2004 to replace PCI and PCI-X. It uses serial instead of parallel communication and is scalable, allowing for higher maximum system bandwidth. The presentation discusses the history of expansion card standards leading to PCIe, including ISA, EISA, VESA, PCI, and PCI-X. It also covers key aspects of PCIe such as the root complex, endpoints, switches, lanes, bus:device.function notation, enumeration, and address spaces such as configuration space.
This document provides an overview of the I2C communication protocol. It describes that I2C is a serial communication protocol used to connect slow devices like EEPROMs and ADCs. It can operate at speeds from 100 kbps to 5 Mbps and supports both single master-multi slave and multi master-multi slave configurations. The document outlines the electrical characteristics, bus features, data frame structure, data transfer process, clock synchronization, arbitration and advantages of the I2C protocol.
The document describes the AMBA 3 APB protocol. It has an unpipelined design to reduce complexity and power consumption. Transfers take at least two cycles with the first being a setup phase and second an access phase controlled by the PENABLE signal. Slaves can extend transfers using the PREADY signal. Errors are indicated by PSLVERR. The protocol defines read and write transfers with or without wait states.
The document describes conventions and signals used in the AMBA 3 APB protocol specification version 1.0. It summarizes write and read transfer procedures, including optional wait states using the PREADY signal. Error responses are also described. The operating states of the APB include IDLE, SETUP, and ACCESS states. PREADY controls exiting the ACCESS state.
The AXI protocol specification describes an advanced bus architecture with burst-based transactions using separate address/control and data phases over independent channels. It supports features like out-of-order transaction completion, exclusive access for atomic operations, cache coherency, and a low power interface. The AXI protocol is commonly used in System-on-Chip designs for high performance embedded processors and peripherals.
Dual-ported RAM allows reads and writes from multiple sources simultaneously, unlike single-ported RAM which allows only one access at a time. It increases bandwidth and reduces design complexity compared to alternatives. Dual-ported RAM is commonly used to enable independent communication between two processors, such as in set-top boxes to transmit and store digital television programs between a CPU and peripheral components.
The document discusses the I2C communication bus protocol. It describes the I2C bus concept of using two bi-directional lines (SDA and SCL) to allow devices with unique addresses to communicate as masters or slaves. The document outlines the I2C communication protocol including START/STOP conditions, byte format, acknowledgment, synchronization, arbitration, and 7-bit and 10-bit addressing schemes. Key aspects of the I2C bus such as typical transfer rates, hardware connections, and terminology are also summarized.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) communication. It describes how UARTs allow for asynchronous serial communication between devices using only 2 wires by converting parallel data to serial and vice versa. The UART communication process involves a transmitting UART adding start, stop and optionally parity bits to data before transmitting it serially bit-by-bit to a receiving UART which reconstructs the parallel data. It also discusses the TTL and RS-232 physical layer standards for UART.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
The document discusses various methods for automatic test pattern generation (ATPG) in testing VLSI circuits, including:
1) Exhaustive and pseudo-exhaustive methods that test all possible patterns but are infeasible for large circuits.
2) Random and weighted random methods that provide confidence in detecting faults but quality depends on the circuit.
3) Deterministic methods like Boolean difference that compute test vectors to detect specific faults more efficiently than examining all vectors.
4) ATPG uses a two-phase approach - random pattern generation and fault simulation initially to detect many faults easily, followed by targeted deterministic pattern generation to detect remaining faults.
its only for learning purpose for beginners who wants to understand this protocol.
Life is all about learning, hope u will enjoy in this my PPT.
for any suggestion your always welcome .
This document provides an overview of the I2C protocol. It describes that I2C was designed by Philips in the 1980s to allow communication between components on the same circuit board. It has since been migrated to NXP and expanded to support higher bus speeds and lower voltages. The document outlines the I2C architecture as a half-duplex, synchronous, multi-master bus using a serial data line and serial clock. It defines I2C nodes can function as a master or slave and transmit or receive data. Electrical characteristics, start/stop conditions, packet formats, clock stretching, arbitration and multi-byte transactions are also summarized.
MIPI DevCon 2016: A Developer's Guide to MIPI I3C ImplementationMIPI Alliance
In this presentation, Intel's Ken Foust, MIPI Sensor Working Group Chair, provides early adopters of MIPI I3C with targeted guidance on how to ensure a successful and efficient implementation of MIPI I3C in their products.
Leveraging I2C as a foundation, many components of MIPI I3C will be familiar to implementers, but with guidance provided here, viewers will gain a clearer understanding of MIPI I3C’s new innovative features, how they will improve their systems, and what considerations should be made to fully leverage them.
The document describes the I2C (Inter-Integrated Circuit) bus interface. I2C is a digital communication protocol used to connect integrated circuits on the same circuit board. It uses just two bidirectional open-drain lines - serial data (SDA) and serial clock (SCL). Devices on the I2C bus can operate as either a master or slave. The master device initiates and controls data transfers. Slave devices respond to the master's commands. The document outlines the electrical considerations, addressing schemes, data transfer protocols, and how to implement I2C on a PIC18F25K22 microcontroller.
The document discusses various ATPG (Automatic Test Pattern Generation) methods and algorithms. It provides an introduction to ATPG, explaining that ATPG generates test patterns to detect faults in circuits. It then covers major ATPG classifications like pseudorandom, ad-hoc, and algorithmic. Several algorithmic ATPG methods are described, including the D-algorithm, PODEM, FAN, and genetic algorithms. Sequential ATPG is more complex due to memory elements. The summary reiterates that testing large circuits is difficult and many ATPG methods have been developed for combinational and sequential circuits.
The PIC microcontroller uses a Harvard architecture with separate program and data memories. It has a CPU with an ALU, memory unit, and control unit. The memory includes program memory to store instructions, data memory including registers for temporary data storage, and EEPROM for storing variables. It has advantages like a small instruction set, low cost, and built-in interfaces like I2C, SPI, and analog components.
The document describes the Serial Peripheral Interface (SPI) protocol which allows for full duplex synchronous serial communication between a master and slave device using 4 pins - MOSI, MISO, SCK, and an optional SS pin. It details the SPI registers for control, status, and data and provides examples of SPI communication with peripherals like digital pots and shift registers. Common issues like conflicts with programming interfaces and ensuring proper chip select signaling are also covered.
Microcontrollers are small computers that integrate RAM, ROM, I/O ports and other components onto a single chip. They are used in applications where cost, power and space are critical. The document compares microprocessors and microcontrollers, noting that microcontrollers have all components on one chip while microprocessors have separate chips. It then describes the typical internal blocks of a microcontroller, including the CPU, memory, I/O ports, timers and serial ports. Block diagrams show the connections between these internal components.
I2c protocol - Inter–Integrated Circuit Communication ProtocolAnkur Soni
This document provides an overview of the I2C communication protocol. It describes how I2C uses only two wires (SDA and SCL) to allow data transmission between an I2C master and multiple I2C slave devices. The document explains the I2C message structure, including the start condition, address frame, read/write bit, data frames, ACK/NACK bits, and stop condition. It also discusses the advantages of I2C, such as supporting multiple masters/slaves and error checking, and disadvantages like slower speeds compared to SPI. Real-life uses of I2C include connections to OLED displays, sensors, and other peripherals.
I2C is a serial communication protocol used to connect low-speed peripherals to processors and microcontrollers. It was developed by Philips in the 1980s for use in televisions. I2C uses just two bidirectional open-drain lines: serial data line (SDA) and serial clock line (SCL). Devices can operate as master or slave devices and have a 7-bit address. Communication is initiated by the master which controls the clock signal. Data is transferred in one byte packets with acknowledgement from the receiver.
Serial Peripheral Interface (SPI) is a communication protocol developed by Motorola for serial communication. It uses a master-slave architecture with 4 connection wires - MOSI, MISO, SCLK, and SS. The master device controls the clock signal and initiates data transfer to and from the slave devices. SPI allows for full duplex communication at high speeds and is commonly used with peripherals like converters, memories, sensors, and displays. While it provides high throughput, SPI requires more pins than alternatives like I2C and does not have hardware flow control or slave acknowledgement.
The document describes the verification of an SPI master core using UVM. It provides details on the SPI protocol, the master core architecture and features, testbench components like agents and scoreboard, testcases that were run, and two bugs that were discovered. The verification covered functionality like different data transfer configurations and achieved 92.85% coverage of the design.
Mux and demux done in cadence with picsdinesh aitha
This document summarizes the implementation of a multiplexer and demultiplexer on Cadence software. It discusses the theory behind multiplexers and demultiplexers, provides their truth tables, and describes creating the main and testbench modules using dataflow and gate level models. Screenshots and waveforms are shown to verify the multiplexer and demultiplexer designs. The student learned how to implement these logic circuits in Cadence through this experiment.
Protocol layers are a hierarchical model of network or communication functions. The divisions of the hierarchy are referred to as layers or levels, with each layer performing a specific task. In addition, each protocol layer obtains services from the protocol layer below it and performs services for the protocol layer above it. The Bluetooth system divides communication functions into protocol layers.
The Bluetooth system consists of many existing protocols that are directly used or have been adapted to the specific use of the Bluetooth system. Protocols are often divided into groups that are used for different levels of communication (a protocol stack). Lower level protocols (such as protocols that are used to manage a radio link between specific points) are only used to create, manage, and disconnect transmission between specific points. Mid-level protocols (such as transmission control protocols) are used to create, manage, and disconnect a logical connection between endpoints that may have multiple link connections between them. High level protocols (application layer protocols) are used to launch, control, and close end-user applications.
Some of the layers associated with the Bluetooth system include the baseband layer (physical layer), link layer, host controller interface (HCI), logical link control applications protocol (L2CAP), RF Communications protocol (RFCOMM), Object Exchange (OBEX), and service discovery.
This ppt explains in brief what actually is arm processor and it covers the first 3 chapters of book "ARM SYSTEM DEVELOPERS GUIDE". The 3 chapters include the history,architecture,instruction set etc.
Inheritance allows a derived class to inherit properties from a base or parent class. A derived class inherits attributes and behaviors of the base class and can add its own attributes and behaviors. There are different types of inheritance including single, multilevel, multiple, hierarchical, and hybrid inheritance. Inheritance promotes code reuse and reduces development time.
This document discusses some of the problems that can arise with multiple inheritance in object-oriented programming, including name ambiguity when classes have methods with the same name, issues with inheritance from common ancestors, and how inner classes can provide an alternative to multiple inheritance without the same semantic problems. It provides examples and potential solutions to demonstrate these problems.
The document provides an introduction to the C programming language and algorithms. It begins with an overview of C and its history. It then defines key concepts like keywords, data types, qualifiers, loops, storage classes, decision statements, and jumps. Examples of algorithms are provided for common problems like adding two numbers. Pattern printing algorithms are given as homework exercises. The document discusses where C is used and explains what a programming language and algorithms are. It emphasizes the importance of understanding requirements before implementation.
Object-Oriented Design: Multiple inheritance (C++ and C#)Adair Dingle
Software Design provides options for structural relationships, such as composition vs. inheritance. Each such option defines malleable and stable characteristics of class dependencies and interface provisions. Software designers must evaluate the short- and long-term costs and benefits of design decisions, such as the simulation of inheritance with composition.
Coming up with optimized C program for Embedded Systems consist of multiple challenges. This presentation talks about various methods about optimizing C programs in Embedded environment. It also has some interesting tips, Do's and Dont's that will offer practical help for an Embedded programmer.
This document provides an overview of how to use I2C communication with AVR microcontrollers. It describes the basic I2C protocol using SCL and SDA lines. It explains that one microcontroller must act as the master that can send data to multiple slave devices using their individual addresses. Example code is provided to initialize I2C on an Arduino Uno and send data from a master to light an LED connected to a slave device. Registers for I2C communication on the ATmega168 microcontroller are also outlined.
This document discusses various techniques for optimizing code on ARM processors, including using conditional instructions, benchmarking with cycle counts, utilizing hardware features like multiplication and DMA, choosing optimal data structures and algorithms, and using mutexes and exclusive monitors for thread synchronization. Some key points covered are using bitwise operations instead of shifts/masks when possible, structs for packing data efficiently in memory, and preferring to reuse existing libraries over reimplementing functionality.
* What are Embedded Systems?
* C for Embedded Systems vs. Embedded C.
* Code Compilation process.
* Error types.
* Code Compilation using command line.
This document discusses various techniques for code optimization at the compiler level. It begins by defining code optimization and explaining that it aims to make a program more efficient by reducing resources like time and memory usage. Several common optimization techniques are then described, including common subexpression elimination, dead code elimination, and loop optimization. Common subexpression elimination removes redundant computations. Dead code elimination removes code that does not affect program output. Loop optimization techniques like removing loop invariants and induction variables can improve loop performance. The document provides examples to illustrate how each technique works.
The document discusses various protocols used in Internet of Things (IoT). It begins with defining IoT and how it works. It then discusses the current status and future of IoT. The major sections of the document are on IoT data link protocols like IEEE 802.15.4, WirelessHART, Z-Wave, and Bluetooth Low Energy. It also covers network layer routing protocols such as RPL and CORPL, and network layer encapsulation protocols.
The document discusses the SPI (Serial Peripheral Interface) bus protocol. It describes SPI as a synchronous serial communication interface used for short-distance communication between a master and multiple slaves. Key points:
1) SPI uses separate clock and data lines to keep the master and slaves in sync for transmission. This eliminates issues with asynchronous protocols like UART having different clock speeds.
2) The master initiates communication by activating a slave's chip select line and generating the clock signal. It then sends and receives data on the MOSI and MISO lines respectively to/from the slave.
3) SPI allows full duplex high-speed communication without packet restrictions or unique slave addresses like in I2C. However,
The SPI (Serial Peripheral Interface) protocol allows for synchronous serial communication between a master and slave device. It uses separate clock and data lines to keep the devices in sync. The master generates the clock signal and selects the slave device using the CS/SS line. Data is simultaneously transmitted in both directions on the MOSI and MISO lines. SPI supports full duplex communication and high speeds. It can connect multiple slave devices to a single master through individual CS lines or daisy chaining. The clock signal ensures reliable transmission without start/stop bits required in asynchronous protocols.
The SPI protocol uses only 2 pins for data transfer called SDI and SDO. It uses the SCLK pin to synchronize data transfer and the CE pin to initiate and terminate transfers. These 4 pins - SDI, SDO, SCLK, and CE - make up the SPI interface. SPI devices communicate serially one bit at a time over these pins.
I2C is a 2-wire serial communication protocol used to connect sensors and peripherals to microcontrollers. It uses just two bidirectional open-drain lines - serial data line (SDA) and serial clock line (SCL). Each device connected to the I2C bus has a unique address and can operate as a transmitter or receiver. The microcontroller acts as the master of the bus by generating the clock signal and initiating data transfers with slave devices by addressing them. Common applications include reading sensor data from an accelerometer over I2C.
SPI (Serial Peripheral Interface) allows for high-speed synchronous serial communication between microcontrollers and peripheral devices. It uses three wires (MOSI, MISO, SCK) to transmit data serially from a master to a slave device. The master device generates a clock signal on SCK to synchronize data transfer. The SS pin is used to select a specific slave device when there are multiple slaves. Common applications of SPI include in-system programming of microcontrollers and communicating with sensors, memory, and other peripherals. An example shows how to use SPI to control LEDs on a slave microcontroller from a master using button inputs.
The document provides an overview of embedded systems and their typical components. It discusses the core architecture of microcontrollers, including operating modes, registers and interrupt handling. It also describes common input/output components like ports, serial interfaces including USART, SPI and I2C, and memory types including SRAM, SDRAM, NOR and NAND flash.
The Master Synchronous Serial Port (MSSP) module allows communication with peripheral devices using either Serial Peripheral Interface (SPI) or Inter-Integrated Circuit (I2C) protocols. In SPI mode, data is synchronously transmitted and received on three pins - Serial Data Out, Serial Data In, and Serial Clock. The MSSP has registers for status, control, and buffering data during read and write operations according to the SPI protocol.
I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). It is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers. Alternatively I²C is spelled I2C (pronounced I-two-C) or IIC (pronounced I-I-C).
Since October 10, 2006, no licensing fees are required to implement the I²C protocol. However, fees are still required to obtain I²C slave addresses allocated by NXP.[1]
Several competitors, such as Siemens AG (later Infineon Technologies AG, now Intel mobile communications), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson), Motorola (later Freescale), and Intersil, have introduced compatible I²C products to the market since the mid-1990s.
SMBus, defined by Intel in 1995, is a subset of I²C that defines the protocols more strictly. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C systems incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus, requiring only minimal reconfiguration.
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include sensors, Secure Digital cards, and liquid crystal displays.
SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.
Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. The SPI may be accurately described as a synchronous serial interface,[1] but it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial communication protocol, but employs differential signaling and provides only a single simplex communication channel.
Embedded systems and robotics by scmandotascmandota
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The bus efficiency is the ratio of useful data bits to total bits transmitted.
At 400 kHz clock rate:
- Clock period is 1/400 kHz = 2.5 μs
- Total bits per transaction is 1 start + 7 address + 1 R/W + 1 acknowledge + 8 data + 1 acknowledge + 1 stop = 20 bits
- Useful data bits is 8
- Data throughput is 8 * 400 kHz = 3.2 kbps
- Bus efficiency is 8/20 = 40%
So at a 400 kHz bus rate, the useful data throughput is 3.2 kbps but the bus efficiency is only 40% due to the overhead of address and acknowledge bits.
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2. Need of Serial Bus Protocol
• Peripheral devices in embedded systems =>
parallel address and data bus => lots of wiring and
requires number of pins => additional decoding logic
required.
• To reduce the pins and wiring => cost => Serial bus
protocol => SPI (4-wire) & I2C (2-wire).
• Penalty => Slower communication.
3. Various Serial Bus Protocol
• UART
• SPI –Embedded System Protocol
• I2C- Embedded System Protocol
• CAN
• USB
• SATA etc..
4. • The Serial Peripheral Interface Bus or SPI bus is a
synchronous serial data link standard named by
Motorola that operates in full duplex mode.
• Devices communicate in master/slave mode where
the master device initiates the data frame. Multiple
slave devices are allowed with individual
slave select (chip select) lines.
5. •During a data transfer the master always sends 8
to 16 bits of data to the slave, and the slave always
sends a byte of data to the master.
• Maximum data bit rate is one eighth of the input
clock rate.
6. • One Central device (Master), initiates communication
with all slaves.
• No address decoding logic required.
• SPI Master wishes to send the data to slave or request
information from the slave, it activates the clock
signal.
• Master generates information on one line (MOSI)
while samples (read) from another line (MISO).
7. SPI Pin Description
• SCLK — Serial Clock (output from master)
• MOSI — Master Output, Slave Input (output from
master)
• MISO — Master Input, Slave Output (output from
slave)
• SS — Slave Select (active low; output from master)
9. Pin Name :SCK (Serial Clock)
Type :Input / Output
• The SPI used clock signal to synchronize the
transfer of data across the SPI interface.
• The SCK is always driven by the master and
received by the slave, The clock is programmable to
be active high or active low.
•The SCK is only active during a data transfer. Any
other time, it is either in its inactive state, or tri-
stated.
10. Pin Name : MISO
(Master in Slave out)
Type : Input / Output
• The MISO signal is a unidirectional signal used to
transfer serial data from the slave to the master.
• When a device is a slave, serial data is output on
this signal.
• When a device is a master, serial data is input on
this signal.
• When a slave device is not selected, the slave
drives the signal high impedance.
11. Pin Name : MOSI
(Master out Slave in)
Type : Input / Output
• The MOSI signal is a unidirectional signal used to
transfer serial data from the Master to the Slave.
•When a device is a Master, serial data is output on
this signal.
• When a device is a Slave, serial data is input on this
signal.
12. Pin Name : SSEL (Slave Select)
Type : Input
• The SPI slave select signal is an active low signal
that indicates which slave is currently selected to
participate in a data transfer.
• Each slave has its own unique slave select signal
input.
•The SSEL must be low before data transactions
begin and normally stays low for the duration of the
transaction.
• If the SSEL signal goes high any time during a data
transfer, the transfer is considered to be aborted.
13. • In this event, the slave returns to idle, and any data that was
received is thrown away. There are no other indications of
this exception.
•This signal is not directly driven by the master. It could be
driven by a simple general purpose I/O under software
control.
•On the LPC2300 the SSEL pin can be used for a different
function when the SPI interface is only used in Master mode.
• For example, pin hosting the SSEL function can be
configured as an output digital GPIO pin and it is also used
to select one of the SPI slaves.
14. Operation
• The SPI bus can operate with a single master
device and with one or more slave devices.
• SPI bus: single master and single slave
15. • If a single slave device is used, the SSEL pin may
be fixed to logic low if the slave permits it.
• Some slaves require the falling edge (high->low
transition) of the slave select to initiate an action
such as the MAX1242 by Maxim, an ADC, that
starts conversion on said transition.
16. Configuration
• Two types multiple slave configuration:
• Typical SPI bus: Master and independent Slaves
• Daisy-Chained SPI bus: Master and cooperative slaves
17. Typical SPI Bus
• With multiple slave devices, an independent
SSEL signal is required from the master for
each slave device (3).
18. • In the independent slave configuration, there is an
independent slave select line for each slave. This is the way
SPI is normally used.
• Since the MISO pins of the slaves are connected together,
they are required to be tri-state pins.
20. • Some products with SPI bus are designed to be capable of
being connected in a daisy chain configuration, the first
slave output being connected to the second slave input, etc.
• The SPI port of each slave is designed to send out during
the second group of clock pulses an exact copy of what it
received during the first group of clock pulses.
•Such a feature only requires a single SSEL line from the
master, rather than a separate SSEL line for each slave.
21. Points
• Not have ack mechanism to confirm receipt of data
and does not have flow control.
• SPI Master, not have knowledge of whether slave
exist or Not
• Not particular addressing scheme.
• Not defined any maximum data rate.
22. Data Transmission
• A typical hardware setup using two shift registers to
form an inter-chip circular buffer
23. • To begin a communication, the master first
configures the Clock, using a frequency less than
or equal to the maximum frequency the slave
device supports.
•Such frequencies are commonly in the range of
1-70 MHz.
•The master then pulls the slave select SSEL low
for the desired chip.
•During each SPI clock cycle, a full duplex data
transmission occurs.
24. •The master sends a bit on the MOSI line; the slave
reads it from that same line
• The slave sends a bit on the MISO line;
the master reads it from that same line
•Transmissions normally involve two shift registers
of some given word size, such as eight bits, one in
the master and one in the slave; they are connected
in a ring.
25. •After that register has been shifted out, the master
and slave have exchanged values.
•Then each device takes that value and does
something with it, such as writing it to memory.
• If there are more data to exchange, the shift
registers are loaded with new data and the process
repeats.
26. Clock Polarity and Phase
• In addition to setting the clock frequency, the
master must also configure the clock polarity and
phase with respect to the data.
• SPI Block Guide names these two options as CPOL
and CPHA respectively, and most vendors have
adopted that convention.
28. At CPOL=0, the base value of the clock is zero
• For CPHA=0, data are read on the clock's
rising edge (low->high transition) and data are
changed on a falling edge (high->low clock
transition).
• For CPHA=1, data are read on the clock's
falling edge and data are changed on a rising
edge.
29. At CPOL=1, the base value of the clock is one
(inversion of CPOL=0)
• For CPHA=0, data are read on clock's falling
edge and data are changed on a rising edge.
• For CPHA=1, data are read on clock's rising
edge and data are changed on a falling edge.
30. CPOL &
CPHA
First data driven Other data
driven
Data
Sampled
0 & 0 Prior to first
SCK rising edge
SCK falling
edge
SCK rising
edge
0 & 1 First SCK rising
edge
SCK rising
edge
SCK falling
edge
1 & 0 Prior to first
SCK falling
edge
SCK rising
edge
SCK falling
edge
1 & 1 First SCK
falling edge
SCK falling
edge
SCK rising
edge
32. • 8-bit data transfer, device is master/slave and setting
of CPHA variable.
•Device, Master => Start of transfer, master having a
data ready to transfer. Activate the clock and begin the
transfer.
•Device, Slave and CPHA=0, transfer start when
SSEL=0.
•Device, Slave and CPHA=1, transfer starts on first
clock edge when slave is selected.
33. Mode Numbers
• The combinations of polarity and phases are
often referred to as modes
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
34. Register Description
• SPI has seven registers, from that programmers
interface for SPI peripheral has five registers.
• The bits in the rest of two TEST registers are
intended for functional verification only.
35. Name Description Access
S0SPCR SPI Control Register.
This register controls the R/W
operation of the SPI.
S0SPSR SPI Status Register.
This register shows the R0
status of the SPI.
36. Name Description Access
S0SPDR SPI Data Register.
This bi-directional
register provides the R/W
transmit and receive
data for the SPI.
37. Name Description Access
S0SPCCR SPI Clock Counter Register.
This register controls the R/W
frequency of a master’s SCK
S0SPINT SPI Interrupt Flag.
This register contains the R/W
interrupt flag for the
SPI interface.
38. (1) SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
1:0 - Reserved, user software
should not write ones to
reserved bits.
39. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
2 BitEnable 0 The SPI controller sends
and receives 8 bits of data
per transfer.
1 The SPI controller sends and
receives the number of bits
selected by bits 11:8.
40. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
3 CPHA Clock phase control
0 Data is sampled on the first
clock edge of SCK.
1 Data is sampled on the
second clock edge of the
SCK.
41. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
4 CPOL Clock polarity control.
0 SCK is active high.
1 SCK is active low.
5 MSTR Master mode select.
0 The SPI operates in Slave
mode.
1 The SPI operates in Master
mode.
42. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
6 LSBF LSB First, controls in which
direction each byte is
shifted when transferred.
0 SPI data is transferred MSB
(bit 7) first.
1 SPI data is transferred LSB
(bit 0) first.
43. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
7 SPIE Serial peripheral interrupt
enable.
0 SPI interrupts are inhibited.
1 A hardware interrupt is
generated each time the
SPIF or MODF bits are
activated.
44. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
11:8 BITS When bit 2 of this register is
1, this field controls the
number of bits per transfer:
1000 8 bits per transfer
1001 9 bits per transfer
1010 10 bits per transfer
1011 11 bits per transfer
45. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
1100 12 bits per transfer
1101 13 bits per transfer
1110 14 bits per transfer
1111 15 bits per transfer
0000 16 bits per transfer
46. SPI Control Register
(S0SPCR - 0xE002 0000)
Bit Symbol Value Description
15:12 - Reserved, user software
should not write ones to
reserved bits.
47. (2) SPI Data Register
(S0SPDR - 0xE002 0008)
• This bi-directional data register provides the
transmit and receive data for the SPI.
• Transmit data is provided to the SPI by writing
to this register.
• Data received by the SPI can be read from this
register.
49. • There is no buffer between the data register and
the internal shift register. A write to the data
register goes directly into the internal shift
register.
• Therefore, data should only be written to this
register when a transmit is not currently in
progress.
50. • Read data is buffered.
• When a transfer is complete, the receive data is
transferred to a single byte data buffer, where it
is later read.
• A read of the SPI data register returns the value
of the read data buffer.
51. SPI Data Register
(S0SPDR - 0xE002 0008)
Bit Symbol Description
7:0 DataLow SPI bi-directional data port.
15:8 DataHigh If bit 2 of the SPCR is 1 and bits
11:8 are other than 1000, some
or all of these bits contain the
additional transmit and receive
bits. When less than 16 bits are
selected, the most significant
among these bits read as zeroes.
52. (3) SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
7 SPIF SPI transfer complete flag.
When 1, this bit indicates when a
SPI data transfer is complete.
When a master, this bit is set at the
end of the last cycle of the transfer.
53. SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
7 SPIF SPI transfer complete flag.
When a slave, this bit is set on the
last data sampling edge of the SCK.
This bit is cleared by first reading
this register then accessing the SPI
data register.
54. SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
6 WCOL Write Collision. When 1, this bit
indicates that a write collision has
occurred. This bit is cleared by
reading this register then accessing
the SPI data register.
55. Exception conditions –Write Collision
• As stated previously, there is no write
buffer between the SPI block bus
interface, and the internal shift register.
• As a result, data must not be written to
the SPI data register when a SPI data
transfer is currently in progress.
56. • The time frame where data cannot be written to the
SPI data register is from when the transfer starts,
until after the status register has been read when the
SPIF status is active.
•If the SPI data register is written in this time frame,
the write data will be lost, and the write collision
(WCOL) bit in the status register will be activated.
57. SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
5 ROVR Read overrun. When 1, this bit
indicates that a read overrun has
occurred. This bit is cleared by
reading this register.
58. Exception conditions –Read Overrun
• A read overrun occurs when the SPI block internal
read buffer contains data that has not been read by the
processor, and a new transfer is completed.
• The read buffer containing valid data is indicated by
the SPIF bit in the status register being active.
59. Exception conditions –Read Overrun
•When a transfer completes, the SPI block needs to
move the received data to the read buffer.
• If the SPIF bit is active (the read buffer is full),
the new receive data will be lost, and the read
overrun (ROVR) bit in the status register will be
activated.
60. SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
4 MODF Mode fault. when 1, this bit
indicates that a Mode fault error
has occurred. This bit is cleared
by reading this register, then
writing the SPI Control register.
61. Exception conditions –Mode Fault
• If the SSEL signal goes active, when the SPI
block is a master, this indicates another master has
selected the same device to be a slave. This
condition is known as a mode fault.
• When a mode fault is detected, the mode fault
(MODF) bit in the status register will be activated.
62. SPI Status Register
(S0SPSR - 0xE002 0004)
Bit Symbol Description
3 ABRT Slave abort. When 1, this bit
indicates that a slave abort has
occurred. This bit is cleared by
reading this register.
2:0 - Reserved, user software should not
write ones to reserved bits.
63. Exception conditions –Slave Abort
• A slave transfer is considered to be aborted,
if the SSEL signal goes inactive before the
transfer is complete.
• In the event of a slave abort, the transmit and
receive data for the transfer that was in
progress are lost, and the slave abort(ABRT)
bit in the status register will be activated.
64. SPI Interrupt Register
(S0SPINT - 0xE002 001C)
• This register contains the interrupt flag for the
SPI interface.
Bit Symbol Description
0 SPI SPI interrupt flag. Set by the SPI
Interrupt interface to generate an interrupt.
Flag Cleared by writing a 1 to this bit.
7:1 - Reserved, user software should
not write ones to reserved bits.
65. SPI Clock Counter Register
(S0SPCCR - 0xE002 000C)
• This register controls the frequency of a
master’s SCK.
• The register indicates the number of PCLK
cycles that make up an SPI clock.
• The value of this register must always be
an even number. As a result, bit 0 must always
be 0.
67. Configuration - Master operation
• The following sequence describes how
one should process a data transfer with
the SPI block when it is set up to be the
master.
• This process assumes that any prior
data transfer has already completed.
68. Configuration - Master operation
1. Set the SPI Clock counter register to
the desired clock rate.
2. Set the SPI Control register to the
desired settings.
3. Write the data that transmitted to the
SPI data register. This write starts the
SPI data transfer.
69. Configuration - Master operation
4. Wait for the SPIF bit in the SPI status
register to be set to 1. The SPIF bit
will be set after the last cycle of the
SPI data transfer.
5. Read the SPI status register.
70. Configuration - Master operation
6. Read the received data from the SPI
data register (optional).
7.Go to step 3 if more data is required
to transmit.
71. Configuration - Master operation
NOTE:
• A read or write of the SPI data register
is required in order to clear the SPIF
status bit.
• Therefore, if the optional read of the
SPI data register does not take place, a
write to this register is required in
order to clear the SPIF status bit.
72. Configuration - Slave operation
• The following sequence describes how
one should process a data transfer with
the SPI block when it is set up to be the
slave.
• This process assumes that any prior
data transfer has already completed.
73. Configuration - Slave operation
1. Set the SPI control register to the
desired settings.
2. Write the data to transmitted to the SPI
data register (optional). Note that this
can only be done when a slave SPI
transfer is not in progress.
74. Configuration - Slave operation
3. Wait for the SPIF bit in the SPI status
register to be set to 1. The SPIF bit
will be set after the last sampling
clock edge of the SPI data transfer.
4. Read the SPI status register.
75. Configuration - Slave operation
5. Read the received data from the SPI
data register (optional).
6. Go to step 2 if more data is required to
transmit.
76. Configuration - Slave operation
NOTE:
• A read or write of the SPI data register
is required in order to clear the SPIF
status bit.
• Therefore, at least one of the optional
reads or writes of the SPI data register
must take place, in order to clear the
SPIF status bit.
77. SPI- Master (C-Code)
• #Include <LPC2300.h>
• Void init (void)
• # define SPIF (1<<7)
• # define data 0xC1
• int main ()
• {
• Init(); // function call
• While (1)
• {
• SPDR= data; // write data out
• While (!(SPSR& SPIF)) { }
• }
• }
• Void init () // fun declared
• {
• PINSEL0=0xAA000;
(SCK1, SSEL1, MOSI1,MISO1)
• VBPDIV=0x1;// set PCLK to
same as CCLk
• SPCR= 0x20;// device selected
master
• }
81. Advantages
• Full duplex communication
• Higher throughput than I²C
• Complete protocol flexibility for the bits
transferred
* Not limited to 8-bit words
* Arbitrary choice of message size,
content, and purpose
82. Advantages
• Extremely simple hardware interfacing
* Typically lower power requirements than
I²C due to less circuitry
* No arbitration or associated failure modes
* Slaves use the master's clock, and don't
need precision oscillators
* Transceivers are not needed
83. Disadvantages
• Requires more pins on IC packages than
I²C, even in the "3-Wire" variant
• No hardware flow control
• No hardware slave acknowledgment (the
master could be "talking" to nothing and not
know it)
84. Disadvantages
• Supports only one master device
• Only handles short distances compared
to RS-232, RS-485, or CAN-bus
85. Applications
SPI is used to talk to a variety of
peripherals, such as:
•Sensors: Temperature, pressure, ADC,
touch-screens
•Control devices: audio codecs, digital
potentiometers, DAC
86. Applications
• Memory: flash and EEPROM
• Real-time clocks
• LCD displays, sometimes even for
managing image data
• Any MMC or SD card