This document provides an overview of the I2C communication protocol. It describes that I2C is a serial communication protocol used to connect slow devices like EEPROMs and ADCs. It can operate at speeds from 100 kbps to 5 Mbps and supports both single master-multi slave and multi master-multi slave configurations. The document outlines the electrical characteristics, bus features, data frame structure, data transfer process, clock synchronization, arbitration and advantages of the I2C protocol.

1. I2C - Inter Integrated Circuit
G.Sunodh Kumar
Design Verification Enginner

2. I2C
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• I2C is Serial Communication Protocol & data transfered bit by bit
• It was first developed by Philips Semiconductors
• It provides the good support to slow devices like EEPROM,ADC..
• Additionally, an I2C bus is used in the various control architecture, for
example, SMBus (System Management Bus), PMBus (Power Management
Bus), IPMI (Intelligent Platform Management Interface) etc.
• Speed : Mode Baud Rate
Standard Mode 100 kbps
Fast Mode 400 kbps
High Speed Mode 3.4 Mbps
Ultra Fast Mode 5 Mbps

3. • It support Single Master - Multi Slave & Multi Master - Multi Slave

4. Electrical Characteristics
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• I2C uses an open-drain/open-collector with an input buffer on the same line, which
allows a single data line to be used for bidirectional data flow
• Another advantage is connecting multiple Open
Collector outputs together in single line results in
“Wired ANDed”(For Clock Synchronization &
Stretching)
• Pull-up resistor on the line is responsible for pulling
the bus voltage up to the power rail. this means that the
bus will never run into a communication issue where
one device may try to transmit a high, and another
transmits a low, causing a short (power rail to ground).
I2C requires it for Aribitraction

5. I2C Bus Features
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• In I2C only two buses are required for the communication,
• Serial data bus (SDA)
• Serial clock bus (SCL).
• Each Salve has unique address to communicate with a master.
• In I2C, Alway’s communication is started by the master.
• Ability of the arbitration and collision detection.
• I2C is the 8-bit oriented serial bidirectional communication with
different speed mode in I2C
• It i worked in Half-Duplex mode

6. Data Frame overview of I2C protocol
• With I2C, data is transferred in messages. Messages are broken up into frames of data.
• Each message has an address frame that contains the binary address of the slave, and
one or more data frames that contain the data being transmitted.
• The message also includes start and stop conditions, read/write bits, and ACK/NACK
bits between each data frame
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7. Data Frame overview of I2C protocol
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• Start Condition: SDA line switches from a high voltage to low voltage level before
the SCL line switches from high to low.
• Stop Condition: SDA line switches from a low voltage to high voltage level before
the SCL line switches from low to high.
• A START and STOP condition always asserted by the master.

8. Address R/W Description
0000 000 0 General call address
0000 000 1 Start byte
0000 001 x CBUS address
0000 010 x Reserved for different bus formats
0000 011 0 Reserved
0000 1xx x High speed mode
0000 0xx x 10-bit address
0000 1xx X Reserved
Special addresses used in the I2C network
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• In Slave address bits are used to address a specific slave device on the bus. 7 bit
address let the master to address maximum of 128 slaves on the bus. Although address
0000 000 is reserved for general call and all address of the format 1111 xxx are
reserved in many devices. That means 119 devices can share an I2C bus. In I2C bus the
MSB of the address is transmitted first.

9. I2C Transcation - Data Transfer Sequence
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• Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH
or LOW state of the data line can only change when the clock signal on the SCL line is
LOW,One clock pulse is generated for each data bit transferred.

10. Data Frame of I2C protocol
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• Repeat Start Condition
In a multi-master configuration, there is the possibility for the master to own the
bus in order to make several transactions without being interrupted by another master. In
this case is used what is called a Repeated START condition.

11. Acknowledgement Scheme in I2C protocol
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Below are some scenario, where NACK bit is generated.
• When the receiver is unable to receive or transmit the data, in that situation it
generates a NACK bit to stop the communication.
• During the communication, if the receiver gets any data or commands which are not
understood by the receiver then it generates a NACK bit.
• During the transfer, if the receiver performs any real-time operation and not able to
communicate with master then assert a NACK bit.
• When Master is a receiver and reads the data from the slave, then after the reading of
whole data it asserts a NACK bit on data lines to stop the communication.
• If there is no device present in the I2c bus of the same address which is transmitted by
the master, then the master will not get the acknowledge by any slave and treat this
situation as NACK.

12. I2C Transcation - Data Transfer from Master to Slave
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• A master device sends the sequence S ADDR W and then waits for an acknowledge bit (A)
from the slave which the slave will only generate if its internal address matches the value
sent by the master. If this happens then the master sends DATA and waits for acknowledge
(A) from the slave. The master completes the byte transfer by generating a stop bit (P) (or
repeated start).

13. I2C Transcation - Data Transfer from Slave to Master
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• A similar process happens when a master reads from the slave but in this case, instead of
W, R is sent. After the data is transmitted from the slave to the master the master sends the
acknowledge (A). If instead the master does not want any more data it must send a not-
acknowledge which indicates to the slave that it should release the bus. This lets the master
send the STOP or repeated START signal.

14. Clock Stretching in I2C protocol
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• One of the features of the I²C protocol is clock stretching. It is a kind of flow control.
If an addressed slave device is not ready to process more data it will stretch the clock
by holding the clock line (SCL) low after receiving (or sending) a bit of data so that
the master will not be able to raise the clock line (because devices are wire-ANDed)
and will wait until the slave releases the SCL line to show it is ready for the next bit.

15. Clock Synchronization in I2C protocol
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• I2c is synchronous communication, in which clock is always generated by the master
and this clock is shared by both master and slave.
• In the case of multi-master, all master generate their own SCL clock, hence it is
necessary that clock of all master should be synchronized. In the I2C, this clock
synchronization is done by Wired ANDed logic.

16. Aribitraction in I2C protocol
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This diagram conveys the basis of I2C arbitration; the process occurs as follows:
• Both masters generate a start bit and proceed with their transmissions.
• If the masters happen to choose the same logic levels, nothing happens.
• As soon as the masters attempt to impose different logic levels, the master driving the
signal low is proclaimed the winner; the loser detects the logic mismatch and
abandons its transmission.

17. Aribitraction in I2C protocol
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Take a moment to appreciate the simplicity and efficacy of this arrangement:
• The winner continues its transmission without interruption—no corrupted data, no
driver contention, no need to restart the transaction.
• Theoretically the loser could monitor the slave address during the arbitration process
and actually make a proper response if it happens to be the addressed slave.
• If the competing masters are both requesting data from the same slave, the arbitration
process does not unnecessarily interrupt either transaction—no mismatch will be
detected, and the slave will output its data to the bus such that multiple masters can
receive it.

18. Advantages of I2C communication protocol
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• It is the synchronous communication protocol, so no need of precise oscillators for the
master and slave.
• It requires only two wire, one wire for the data (SDA) and other wire for the clock
(SCL).
• It provides the flexibility to the user to select the transmission rate as per the
requirements.
• In I2C Bus, each device on the bus is independently addressable.
• It follows the master and slave relationships.
• It has the capability to handle the multiple masters and multiple slaves on the I2C Bus.
• I2C has some important features like arbitration, clock synchronization, and clock
stretching.
• I2C provide ACK/NACK (acknowledgment/ Not-acknowledgement) features which
provide the help in error handling.

19. Some important limitation of I2C communication protocol
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• It consumes more power than other serial communication busses due to open-drain
topology.
• It is good only for the short distance.
• I2C protocol has some limitation for the number of slaves, the number of the slave
depends on the capacitance of the I2C bus.
• It only provides few limited communication speed like 100 kbit/s,400 kbit/s etc.
• In I2c, devices can set their communication speed, slower operational devices can
delay the operation of faster speed devices.
• The Size of the data frame is limited to 8 bits

20. Reference :
• https://aticleworld.com/i2c-bus-protocol-and-interface/
• http://karuppuswamy.com/wordpress/2015/06/24/what-is-open-collector-output-pull-
uppull-down-resistor-and-tri-state-output/
• http://www.ti.com/lit/an/slva704/slva704.pdf
• https://www.artekit.eu/i2c-communication-protocol/
• https://www.best-microcontroller-projects.com/i2c-tutorial.html

21. Thank You