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Mr.Tejas Dave Chovatiya Ravi Jitendra Edle Sachin Nigam Prepared by:- Guide by:- “ I2C Bus Protocol Implementation” THAKUR INSTITUTE OF CAREER ADVANCEMENT
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],What is I2C?
Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C  Master Core  WISHBORN Interface Prescale  Register Command Register Transmit Register Status  Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator
External connection
Register List Status Register R 8 100 SR Command Register W 8 011 CR Receive Register R 8 110 RXR Transmit Register W 8 101 TXR Control Register RW 8 Null CTR Clock Prescale Register Hi-byte RW 8 001 PRERhi Clock Prescale Register Lo-byte RW 8 000 PRERlo Description Access Width Address Name
  Control register
Transmit Register Receive Register
Command Register
Status Register
I 2 C Bus Configuration ,[object Object],[object Object],[object Object],[object Object]
I2C Protocol  1. Master sends start condition (S) and controls the clock signal 2. Master sends a unique 7-bit slave device address 3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit 4. Slave with matching 7-bit device address always sends acknowledge bit (ACK)  5. Transmitter (slave or master) transmits 1 byte of data
I 2 C Protocol (cont.) 6. Receiver issues an ACK bit for the byte received 7. Repeat 5 and 6 if more bytes need to be transmitted 8. Master always sends stop condition (P) a. For write transaction (master transmitting), master issues stop condition (P) after last byte of data. b. For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
[object Object],[object Object],[object Object],[object Object],I 2 C Signals
  Bit Command Controller I
A B I 2 C Signals C D I
Write 1 byte of data  to a slave ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Read 1 byte of data  to a slave  ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
I 2 C Features ,[object Object],[object Object],[object Object]
Clock Synchronization ,[object Object],[object Object]
[object Object],[object Object],Multiple Devices
[object Object],Multi-Master Support
[object Object],[object Object],Advantages Of I2C
Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C  Master Core  WISHBORN Interface Prescale  Register Command Register Transmit Register Status  Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator
References ,[object Object],[object Object],[object Object],[object Object],[object Object]
Thank you

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I2C

  • 1. Mr.Tejas Dave Chovatiya Ravi Jitendra Edle Sachin Nigam Prepared by:- Guide by:- “ I2C Bus Protocol Implementation” THAKUR INSTITUTE OF CAREER ADVANCEMENT
  • 2.
  • 3. Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C Master Core WISHBORN Interface Prescale Register Command Register Transmit Register Status Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator
  • 5. Register List Status Register R 8 100 SR Command Register W 8 011 CR Receive Register R 8 110 RXR Transmit Register W 8 101 TXR Control Register RW 8 Null CTR Clock Prescale Register Hi-byte RW 8 001 PRERhi Clock Prescale Register Lo-byte RW 8 000 PRERlo Description Access Width Address Name
  • 6. Control register
  • 10.
  • 11. I2C Protocol 1. Master sends start condition (S) and controls the clock signal 2. Master sends a unique 7-bit slave device address 3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit 4. Slave with matching 7-bit device address always sends acknowledge bit (ACK) 5. Transmitter (slave or master) transmits 1 byte of data
  • 12. I 2 C Protocol (cont.) 6. Receiver issues an ACK bit for the byte received 7. Repeat 5 and 6 if more bytes need to be transmitted 8. Master always sends stop condition (P) a. For write transaction (master transmitting), master issues stop condition (P) after last byte of data. b. For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
  • 13.
  • 14. Bit Command Controller I
  • 15. A B I 2 C Signals C D I
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24. Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C Master Core WISHBORN Interface Prescale Register Command Register Transmit Register Status Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator
  • 25.