This document discusses sequential circuit design and various types of flip-flops. It begins with explaining a one bit memory cell using two cross-coupled inverters. It then describes an SR latch and how adding Set and Reset inputs addresses issues with the basic latch. SR, JK, D, T, and clocked flip-flops are defined along with their truth tables. Implementation of different flip-flops from one another is covered. Counters using flip-flops are introduced as synchronous and asynchronous types. Preset and Clear inputs for flip-flops are explained. Finally, the relationship between the number of states in a counter and the number of flip-flops used is defined.

1. Sanjivani Rural Education Society’s
Sanjivani College of Engineering, Kopargaon-423 603
(An Autonomous Institute, Affiliated to Savitribai Phule Pune University, Pune)
NACC ‘A’ Grade Accredited, ISO 9001:2015 Certified
Department of Computer Engineering
(NBA Accredited)
Prof. S.A.Shivarkar
Assistant Professor
E-mail : shivarkarsandipcomp@sanjivani.org.in
Contact No: 8275032712
Subject- Digital Electronics and Data Communication
(CO204)
Unit 3- Sequential Circuit Design-1

2. One bit memory cell
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• One bit memory cell is designed using two cross
coupled invertors N1 and N2. (NAND gates are used
as invertors).
• It is known as bistable element as it contain only two
states logic 1 state (HIGH) and logic 0 state (LOW).
• Let us assume that Q=1
• Which is input to N2.
• So output of N2 is 0 which is input for N1.
• So output of N1 is 1 which confirms our
assumption.
• Similarly second assumptions can be verified.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

3. One bit memory cell cont..
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• Conclusion
• The outputs Q and Q’ are always complementary.
• The circuit has two stable states.
• If circuit is in 1 state then it continues to remain
in this state.
• Similarly if it is in 0 state then it continues to
remain in this state.
• So it is one bit memory cell.
• Also called as latch.

4. SR Latch
• No way of entering desired digital
information in latch shown in Fig. 1
• When power is switched ON the
circuit will switch to one of the
stable state either 1 or 0. Can not
predict!!
• So we have modified circuit as
shown in Fig. 2
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Fig. 1
Fig. 2

5. SR Latch cont..
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
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• Case 1
• S=R=0
• Assume Initial Q = 0
• then Next Q=0
• Assume Initial Q = 1
• then Next Q=1
• State does not
change.
Note: If We know that one of
the input of NAND gate is 0
then output of the NAND will
be always 1…
• Case 2
• S=1 and R=0
• Assume Initial Q = 0
• then Next Q=1
• Assume Initial Q = 1
• then Next Q=1
• Set state.

6. SR Latch cont..
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
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Note: If We know that one of
the input of NAND gate is 0
then output of the NAND will
be always 1…
• Case 3
• S=0 and R=1
• Assume Initial Q = 0
• then Next Q=0
• Assume Initial Q = 1
• then Next Q=0
• Reset state.
• Case 4
• S=1 and R=1
• Both Q and Q’ tries
to become 1.
• Invalid. (This
condition is
prohibited)

7. SR Latch cont..
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Summary of operation of SR Latch
S R Qn Qn+1 Remark
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 × Ambiguous
1 1 1 ×
• Case 1
• S=R=0
• State does not
change.
• Case 2
• S=0 and R=1
• Reset state.
• Case 3
• S=1 and R=0
• Set state.
• Case 4
• S=1 and R=1
• Invalid.

8. Clocked SR Flip Flop
• It is often require to set or reset the
memory cell in synchronism with
train of pulse known as clock.
• Such a circuit is called as clocked SR
Flip Flop.
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9. Edge Detector
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10. Clocked SR Flip Flop cont..
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Summary of operation of SR Flip Flop (Positive edge triggered)
CLK S R Qn Qn+1 Remark
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 × Ambiguous
1 1 1 ×

11. Clocked SR Flip Flop cont..
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Summary of operation of SR Flip Flop (Negative edge triggered)
CLK S R Qn Qn+1 Remark
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 × Ambiguous
1 1 1 ×

12. JK Flip Flop
• Similar to SR FF only one major
difference:
• J=K=1 condition does not result in
ambiguous state.
• For this condition (J=K=1) the FF
always goes in opposite state (i.e. if
previous state of FF is 0 then next
state will be 1 and if previous state is
1 then next state will be 0).
• This is called as toggle mode of
operation.
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13. JK Flip Flop cont..
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Operation of JK Flip Flop (Negative edge triggered)
CLK J K Qn Qn+1 Remark
0 0 0 0 No
Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

14. D Flip Flop
• It has only one input D, which stands
for data.
• Block diagram
• Operation
• If D is 0 then Qn+1 will 0.
• If D is 1 then Qn+1 will be 1.
• The level present on D will be stored
in the FF when negative edge is
detected on clock pulse.
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CLK D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1

15. Implementation of D FF
• D FF can easily implemented
using JK FF by adding invertor.
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16. T Flip Flop
• It has only one input T.
• Block diagram
• Operation
• If T is 0 then no change
• IF T is 1 then toggle.
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CLK T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

17. T Flip Flop cont..
• It is obtained from JK FF by connecting J and K inputs together.
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18. Excitation table
• In designing sequential circuits sometimes present state and next
state of the circuit are specified and it is required to find input
condition that will cause desired transition of the state.
• So there is a need of excitation table.
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19. Excitation table of SR FF
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Truth table for SR Flip Flop (Negative edge triggered)
CLK S R Qn Qn+1 Remark
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 × Ambiguous
1 1 1 ×
Excitation table
Qn Qn+1 S R
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0

20. Excitation table of JK FF
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Truth table for JK Flip Flop (Negative edge triggered)
CLK J K Qn Qn+1 Remark
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0
Excitation table
Qn Qn+1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0

21. Excitation table of D FF
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Excitation table
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Truth Table
CLK D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1

22. Excitation table of T FF
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Excitation table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Truth Table
CLK T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

23. Excitation table of T FF
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Excitation table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Truth Table
CLK T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

24. Flip Flop conversion
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25. Flip Flop conversion cont..
• Convert SR FF into D FF
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26. Flip Flop conversion cont..
• Convert SR FF into D FF
• Step1
• Write TT of D FF.
• Step2
• Add two column S and R
in TT of D FF.
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D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
D Qn Qn+1 S R
0 0 0
0 1 0
1 0 1
1 1 1

27. Flip Flop conversion cont..
• Step3
• Combine excitation table
of SR FF in the table
obtained in step 2
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D Qn Qn+1 S R
0 0 0
0 1 0
1 0 1
1 1 1
Excitation table
Qn Qn+1 S R
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0
D Qn Qn+1 S R
0 0 0 0 ×
0 1 0 0 1
1 0 1 1 0
1 1 1 × 0

28. Flip Flop conversion cont..
• Step4
• Neglect Qn+1
• Design required combinational circuit
assuming D, Qn as input and S, R as
output
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D Qn Qn+1 S R
0 0 0 0 ×
0 1 0 0 1
1 0 1 1 0
1 1 1 × 0

29. Flip Flop conversion cont..
• Step5
• Draw K map for S and R
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D Qn S R
0 0 0 ×
0 1 0 1
1 0 1 0
1 1 × 0

30. Flip Flop conversion cont..
• Step6
• Draw logic diagram for Flip Flop conversion
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31. • It is a sequential circuit used for counting.
• It is used for counting particular event.
• Clock is given as a input.
• A circuit used for counting the clock pulses is called as counter.
• Counter is group of FF.
Counter
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32. • Basically there are two types of counter
• Asynchronous counter (Ripple counter)
• Synchronous counter
• In case of Asynchronous counter all the flip flops are not
clocked simultaneously.
• External clock pulse is applied only to first FF and output of first
becomes clock for second, output of second becomes clock for
third and so on.
• In case of Synchronous counter all the flip flops are
clocked simultaneously.
• External clock pulse is applied to all FF
Counter cont..
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33. • No. of FF required?
• 2 bit counter so two FF will be required.
• Type of FF
• T or JK
• Fig. shows 2 bit counter with T FF having
negative edge triggering..
• It will have 4 states (22).
• Inputs of both FF should be at Logic 1 so
that output will toggle.
• External clock pulse is applied to FF A and
its o/p QA is connected to clock input of
FF B.
2 bit Asynchronous (Ripple) Up Counter
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34. • f(QA)=f(CLK)/2
• f(QB)= f(CLK)/4
2 bit Asynchronous Up Counter / Ripple Counter
cont..
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35. • When power is applied, all flip flops comes in random
state.
• In some digital system it is required to set FF when
power is applied..
• In some digital system it is required to reset FF when
power is applied..
• So we have Preset and Clear input in FF..
• These are active low inputs.
• If Preset’=0 then Q=1
• If clear’=0 then Q=0
• These are asynchronous inputs because there
operation is independent of the clock.
Preset and Clear Input in FF
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36. • The counter with N FF can have 2N states.
• For example 2 bit counter has 4 states, 3 bit counter has 8 states.
• If counter has m states then it is called MOD m counter.
• 2 bit counter is MOD 4 counter.
• If MOD m counter is required then number of FF required (N) is determined using following condition.
• m<=2N
• Example
• For MOD 3 counter
• 2 FF
• For MOD 6 counter
• 3 FF
• But using 3 FF we will get 8 states. In MOD 6 counter only 6 states will be used, 2 will be unused.
• The counter is required to reset at the end of 6th clock pulse.
• This is possible by generating logic 0 signal at the end of 6th clock pulse and applying it to clear
input of all FF.
Modulus Asynchronous counter
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37. • Design MOD 6 ripple
counter.
• Using 2 FF not possible
• Using 3 FF it is possible but
required to design RESET
logic.
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Modulus Asynchronous counter cont..

38. IC 7490
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• It is ripple counter IC.
• It is decade counter. (mod 10)
• It consist of 4 FF internally connected together.
• It contain two separate counter i.e MOD 2 and MOD
5.
• These counter can be used as independently or in
combination to provide MOD 10 counter.
• There are two reset input R0(1) and R0(2) both of
which are to be connected to logic 1 for clearing
outputs of counter.
• There are two more reset input R9(1) and R9(2) both
of which are to be connected to logic 1 for setting
counter to 1001.

39. 7490 cont..
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40. 7490 as Decade Counter
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41. Design MOD 6 counter using 7490
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42. • Steps
1. Determine number of FF required and decide
type of FF.
2. Write excitation table for selected FF.
3. Draw state diagram.
4. Prepare circuit excitation table.
5. Prepare K map for each FF input in terms of FF
outputs as input variable.
6. Simplify K map and obtain minimized
expression.
7. Draw final circuit diagram.
Design of Synchronous counter
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43. • Step1:
• 2 bit counter so 2
FF will be required.
Type of FF is T as
given in problem.
• Step2:
• Step3:
Design 2 bit synchronous counter using T FF
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Excitation table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

44. • Step4:
Design 2 bit synchronous counter using T FF
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Present state Next state TB TA
QB QA QB1 QA1
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

45. • Step5:
Design 2 bit synchronous counter using T FF
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Present state Next state TB TA
QB QA QB1 QA1
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

46. • Step7:
Design 2 bit synchronous counter using T FF
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