Digital Electronics

1. Sanjivani Rural Education Society’s
Sanjivani College of Engineering, Kopargaon-423 603
(An Autonomous Institute, Affiliated to Savitribai Phule Pune University, Pune)
NACC ‘A’ Grade Accredited, ISO 9001:2015 Certified
Department of Computer Engineering
(NBA Accredited)
Prof. S.A.Shivarkar
Assistant Professor
E-mail : shivarkarsandipcomp@sanjivani.org.in
Contact No: 8275032712
Subject- Digital Electronics and Data
Communications(CO204)
Unit 4- Sequential Circuit Design-2

2. Register
• Flip flop is used is store 1 bit data.
• A register is simply group of a flip-flop used to store binary number.
• Registers hold larger quantities of data than individual flip-flops.
• Registers are commonly used as temporary storage in a processor.
• Registers find application in variety of digital system including
microprocessor.
• Example
• In 8086 processor 16 bit registers are present which can store 16 bit data. (16 FF will be required)
• Not only used for storage!!
• Sequence generator
• Parallel to serial convertor
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3. Types of Registers
1. Serial In Serial Out(SISO)
2.Serial In Parallel Out(SIPO)
3.Parallel In Parallel Out(PIPO)
4.Parallel In Serial Out(PISO)
5.Bidirectional Shift Register
6.Universal Shift Register
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1. Write
2. Read
IF the registers supports Serial in or Serial out then it is called as Shift Register.

4. Types of Registers
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1. SISO:-Serial In Serial Out
2. SIPO:-Serial In Parallel Out
3. PISO:-Parallel In Serial Out
4. PIPO:-Parallel In Parallel Out
10110 10110
10110
10110
10110
10110
10110
10110

5. SISO
Writing data into SISO register
CLK Data Q1 Q2 Q3 Q4
Initially 1011 0 0 0 0
1 101 1 0 0 0
2 10 1 1 0 0
3 1 0 1 1 0
4 -- 1 0 1 1
• Consider 4 bit SISO
Register.
• 1 Pin for input.
• 1 Pin for output.
• N clock cycle for
writing N bits.
• N-1 clock cycle for
reading N bits.
• When data is read
then data in register is
lost (Destructive
reading).

6. SISO
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N-1 Clock
cycles are
required for
reading data
from SISO
registers!!
Reading data from SISO register
CLK Data Q1 Q2 Q3 Q4 Read data
Initially 0 1 0 1 1 1
1 0 0 1 0 1 11
2 0 0 0 1 0 011
3 0 0 0 0 1 1011

7. SIPO
• 1 Pin for input
• N Pin for N outputs
• N clock cycle for
writing N bits

8. PISO

9. PIPO
• In N bit register number of Input
pins will be N and number of
output pins will be N
• 1 clock cycle for writing N bits

10. Bidirectional Shift Register
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With M=1( shift right operation):-
• 1,3,5,7 AND gates are
enabled and data DR is
shifted to the right when
clock pulses are applied.
With M=0(shift left operation):-
• 2,4,6,8 AND gates are
enabled and allowing
the data at DL to be
shifted to left
Shift
right
Shift
left

11. Universal Shift Registers
• If the register has both shifts(right shift and left shift) and parallel
load capabilities, it is referred to as universal shift register.
• Universal shift registers are used as memory elements in computers.
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S1 S0 Selected Mode
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

12. Universal Shift Registers

13. Shift Register Applications
• Temporary data storage.
• Bit manipulation.
• Serial to parallel convertor.
• Parallel to serial convertor.
• Serial and parallel communications.
• Sequence generator.
• Sequence detector.
• Logical operations.
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14. Ring Counter
• It is one application of Shift Register.
• In Ring counter output of last FF is connected to the input of first FF.
• The FF are connected so that information shift from left to right and back around from Q3 to Q0
• In most cases there is single “1” in the register and it is made to circulate around the register.
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15. Operation of Ring Counter
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• Apply Logic 0 to External Input so that Ring counter enters in its initial state i.e.
(Q3Q2Q1Q0=1000).
• Then apply Logic 1 to External Input.
• Then go on applying one clock pulse so that it enters into its subsequent states as shown in
following diagrams.
• No. of states in Ring counter = No. of flip flops

16. Waveform of 4 bit Ring Counter
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17. Johnson Counter / Twisting Ring / Switch Tail
Counter
• It is another application of Shift register.
• The basic ring counter is modified to produce Johnson counter.
• In Johnson counter inverted output of last FF is connected to input of
first FF.
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18. Operation of Johnson Counter
• Logic 0 should be applied to Clear input of all Flip flop in Johnson counter so that it enters in initial
state (Q2Q1Q0 = 000)
• Then go on applying clock pulse so that Counter enters in its subsequent
states(100,110,111,011,001,000…..)
• On negative edge of each clock pulse level at Q2 shifts into Q1, the level at Q1 shifts into Q0 and
inverse of level at Q0 shifts into Q2.
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19. Waveform of Johnson Counter
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20. 4 bit Johnson counter sequence
No of steps=2*no of flip flops
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4 bit Johnson counter sequence
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
0 0 0 0
5 bit Ring counter sequence

21. Sequence Generator
• A sequence circuit which generates a prescribed sequence of bits in
synchronism with a clock, is referred to as sequence generator.
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22. Design of Sequence generator
• Problem – Design sequence generator for sequence: 0 → 1 → 3 → 4
→ 5 → 7 → 0, using T flip-flop
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23. Steps
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• Draw Sequence
• Find no of flip flops from states
• Write state transition table
• Write flip flops inputs from state transition table
• Find equations for flip flop inputs using k-map
• Draw logic diagram

24. State transition table logic
Present State Next State
0 1
1 3
3 4
4 5
5 7
7 0
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25. State transition table for given sequence
Present state Next state Flip flop inputs
Q3 Q2 Q1 Q3+1 Q2+1 Q1+1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 1 0 1 0
1 1 1 0 0 0 1 1 1
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26. K-map
• Find value of T3, T2, T1 in terms of Q3, Q2, Q1 using K-map
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T3=Q2 T3=Q1 T3=Q2’

27. Logic Diagram
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28. Problem Statement
• Design sequence generator to go through the following states by
using JK flip-flop
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29. Present
state
Next
state
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Present
state
Next state A B C
QA QB QC QA
+
QB
+
QC
+
JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 X X X X X X X X X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 1 0 X 0 1 X 0 X
1 0 1 1 X X X X X X X X
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 X X X X X X X X X
State Transition
Table

30. K-Map
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31. Connection Diagram
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32. Sequence Detector
• A sequence circuit, which detects a prescribed sequence of bits in
synchronism with a clock , is referred to as sequence detector.
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33. Problem statement
• Design sequence detector using JK flip flop to detect the following
sequence:- 1001
State diagram
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Present
state
Next
state
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Present state Next state FF1 FF0
Q1 Q0 X Q1+1 Q0+1 Z J1 K1 J0 K0
0 0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 0 X 1 X
0 1 0 1 0 0 1 X X 1
0 1 1 0 1 0 0 X X 0
1 0 0 1 1 0 X 0 1 X
1 0 1 0 1 0 X 1 1 X
1 1 0 0 0 0 X 1 X 1
1 1 1 0 1 1 X 1 X 0
State Transition
Table

35. K-Map
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36. Sequence detector
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37. Mealy Model
• In Mealy model , both outputs and next state depend both on
primary inputs AND present state.
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38. Problem
• Design 101 sequence detector (Mealy Machine)
• Steps to design 101 Mealy sequence detector:-
Step1:- The state diagram of a Mealy machine:-
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39. Step2:-Code Assignment:-
State diagram after the code assignment:-
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40. Step3:-Make present state/next state table
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41. Step4:-Draw K-maps and then implement the circuit
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42. Moore Model
• In Moore model only next state depends directly on primary inputs
AND present state . Outputs depend only on present state.
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43. Problem
• Design Moore sequence generator to detect a sequence 101
• Steps to detect a sequence 101
Step1:-The state diagram of a Moore machine for 101 detector is:
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44. Step2:-State and Transition table
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45. Step3:- K-maps to determine inputs
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46. Step4:-Circuit diagram for the sequence detector
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47. Difference between Moore and Mealy.
Moore machine Mealy machine
1.Output depends only upon present state. 1.Output depends on present state as well as present
input.
2.If input changes , output does not change 2. If input changes , output also change
3.More number of states are required 3. Less number of states are required
4.They react faster to inputs. 4.They react slower to inputs.
5.Synchronous output and state generation 5.Asynchronous output generation
6.Output is placed on states 6.Output is placed on transitions
7.Easy to design 7.Difficult to design

48. THANKYOU…………………
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