Question bank on digital electronics. Total 194 questions. Covering questions on basics of digital electronics, number systems, digital gates, logic families, the sum of product, the product of sum, boolean theorem, karnaugh map, coders, etc.

1. Sanjay Ghodawat University
School of Technology
Department of Electronics Engineering
Dr. Nilesh Bhaskarrao Bahadure, SGU Page 1
Question Bank
Subject: Digital Electronics
Unit – I, II and III
Short questions
1. What is digital system
2. Explain characteristics of digital IC’s
3. Explain the following terms in details
(a) Speed of operation
(b) Fan – in
(c) Noise Immunity
4. Differentiate between TTL and CMOS Logic
family
5. Explain the following characteristics of digital
IC’s
(a) Figure of Merit
(b) Fan – out
(c) Operating temperatures
(d) Power dissipation
6. What is Boolean algebra?
7. Explain Boolean laws and theorems with truth
table.
8. Explain Demorgan’s theorem with truth table
9. Explain associative, cumulative and
distributive Boolean laws.
10. Explain universal gates in details with suitable
example.
11. Draw and explain all the gates with truth
table.
12. Explain how to generate inverter using two
input EX‐OR and two input EX‐NOR gate
13. Design and implement AND gate, OR gate and
NOT gate using NAND gate only.
14. Design and implement AND gate, OR gate and
NOT gate using NOR gate only.
15. Explain EX‐OR and EX‐NOR gates with truth
table.
16. Explain the significance of digital logic gates in
digital system.
17. Write short notes on integrated circuits.
18. Convert the decimal number 57 into binary.
19. Convert the decimal number 53.625 into
binary
20. Convert the binary number (101111.1101)2
into decimal equivalent.
21. Convert octal numbers (a) 237 (b) 120 to
decimal
22. Covert decimal numbers 115 and 235 into
hexadecimal and octal
23. Multiply the following binary numbers
(a) 1011 and 1101
(b) 100110 and 1001
(c) 1.01 and 10.1
24. Divide the following
(a) 11001 ÷ 101
(b) 11101 ÷ 1100
25. Explain 1’s and 2’s complement method for
subtraction.
26. Subtract (1010)2 from (1111)2 using 1’s and 2’s
complement method. Also subtract using
direct method and compare.
27. Compare 1’s and 2’s complement method.
28. Find 9’s complement of the following decimal
numbers
(a) 19
(b) 146
(c) 469
(d) 4397
29. Perform the following subtraction using 9’s
complement method
(a) 18 – 06
(b) 39 – 23
(c) 34 – 49
(d) 49 – 84
30. Convert following base number to their given
base number
(a) (102)3 = ( )5
(b) (123)4 = ( )2
(c) (10100001)gray code = ( )2
(d) (11001001)gray code = ( )10
(e) (569)10 = ( )11
31. Find 16’s complement of following numbers
(a) 23A

2. Sanjay Ghodawat University
School of Technology
Department of Electronics Engineering
Dr. Nilesh Bhaskarrao Bahadure, SGU Page 2
(b) F02
(c) 67810
(d) 568
(e) (1011001101011)2
(f) A2BC3
32. Convert the following decimal numbers into
its 10’s complement form
(a) 9
(b) 46
(c) 739
33. Subtract the following decimal numbers using
the 10’s complement method
(a) 9 – 4
(b) 24 – 09
(c) 69 – 32
(d) 347 – 265
34. Explain BCD number system in details.
35. Carry out BCD subtraction for (68) – (61) using
10’s complement method.
36. Explain weighted binary codes.
37. Explain the following codes and give the code
values for decimal numbers 0 to 9.
(a) 2421 code
(b) 5421 code
(c) 5211 code
(d) Excess – 3 code
(e) Gray code
38. Explain non – weighted codes
39. Convert (643)10 into excess – 3 code
40. Encode data bits 0101 into a 7 bit even parity
hamming code
41. A 7 bit hamming code is received as 0101101.
What is its correct code?
42. Using Boolean algebra technique, simplify the
following expression
AB + A (B + C) + B (B + C)
43. Using Boolean algebra technique, simplify the
following expression
[AB (C + BD) + A B] C
44. Convert the following Boolean expression into
standard SOP form
A B C + A B + A B C D
45. Implement Y = A B + A + (B + C) using NAND
gates only.
46. Simplify the following Boolean expression
(a) A’BC + A B’ C’ + A’ B’ C’ + A B’ C + A B C
(b) (AB+AC)’ + A’ B’ C
47. Convert the following into standard SOP form
(a) AB + ABC
(b) A B’ C + A’ B’ + A B C’ D
48. Determine the binary value for which the
following standard SOP expression is equal to
1.
ABCD + A B’C’ D + A’ B’ C’ D’
49. Express the function Y = A + B’ C in
(a) Canonical SOP form
(b) Canonical POS form
50. Realize Y = A + B C D’ using NAND gates only
51. Realize Y = (A + C) (A + D’) (A + B + C’) using
NOR gates only
52. Differentiate between 9’s and 10’s
complements.
53. What is gray code? Why it is important.
54. What is a hamming code and how it is used.
55. State the methods used to simplify the
Boolean expression
56. How is the AND multiplication is different
from ordinary multiplication.
57. State and explain the Demorgan’s theorem.
58. Prove Demorgan’s theorem for 4 variable
functions.
59. Prove the distributive property A + BC = (A +
B) (A+C)
60. Prove AB + A’C + BC = AB + A’C using Boolean
algebra theorem.
61. Prove (A + B)(A’ + C)(B + C) = (A+B)(A’ + C)
62. simplify the logic circuit
63. Complement the expression A’B + CD’
64. Find the complement of the expression Y =
ABC +ABC’ + A’B’C + A’BC
65. Obtain the canonical sum of product form
A
C’
B
D

3. Sanjay Ghodawat University
School of Technology
Department of Electronics Engineering
Dr. Nilesh Bhaskarrao Bahadure, SGU Page 3
(a) Y = A + B
(b) Y = AB + ACD
66. Obtain the canonical POS form
(a) Y = (A + B’)(B + C)(A+C’)
(b) Y = A + B’C
67. The voltage waveform shown in the figure are
applied at the inputs of 2 – input AND, OR,
NAND, NOR, EX – NOR, and EX – OR gates.
Determine the output waveform in each case.
68. Four messages are encoded in the following
code words:
Messages Code
M1 01101
M2 10011
M3 00110
M4 11000
Determine the minimum distance of the code.
69. Find out the value of k for converting BCD
code into Hamming code and the bit positions
of the resulting hamming code.
70. What are the applications of Boolean algebra?
71. Explain the terms:
(a) Prime Implicant
(b) Input variable
(c) Minterm
(d) maxterm
72. What is meant by duality in Boolean algebra?
73. Obtain the canonical sum of product and
product of sum of the following expression
F = x1 x2 x3 + x1 x3 x4 + x1 x2 x4
74. Convert f = ABCD + A’BC + B’C’ into a sum of
Minterm by algebraic method
75. Convert f = AB + B’CD into product of
maxterms by algebraic method.
76. What is a universal gate?
77. Explain how the basic gates can be realized
using NAND gates.
78. Explain how the basic gates can be realized
using NOR gates.
79. Realize the logic expression using basic gates
(a) Y = B’ C’ + A’ C’ + A’ B’
(b) Y = (A + B)(A’ + C)(B + D) using basic gates
80. What is mixed or alternate logic?
81. Draw the alternate gate symbols for the basic
and universal gates.
82. Give the mixed logic for the following gates
(a) AND
(b) OR
(c) NOT
Long Questions:
83. Explain the properties of Boolean algebra.
84. Simplify the given logical expressions
(a) AB + BC + B’C
(b) A’B + AB + A’ B’
(c) A+ AB’ + A’B
(d) AB + (AC)’ + AB’C(AB+C)
(e) Y= (A’ + B) (A+ B)
(f) [(AB’+ABC)’+A(B+AB’)]’
(g) Y = ABC +AB’C+ABC’
(h) Y= A’B’C’ +A’BC’+AB’C’+ABC’
(i) (AB+C)(A+B+C)
85. If A’B + CD’ = 0, then prove that AB + C’(A’+D’)
= AB + BD + (BD)’ + A’C’D
86. Simplify the following expression using the K‐
Map for the 4 variables A, B, C and D
Y = m1 + m3 + m5 + m7 + m8 + m9 + m12 + m13
87. Plot the logical expression ABCD + AB’C’D’ +
AB’C + AB on a 4 – variable K map; obtained
the simplified expression from the map.
88. Simplify the expression Y
=∑ 7, 9, 10, 11, 12, 13, 14, 15 , using the K –
map method.
89. Simplify the expression Y = m1 + m5 + m10 +
m11 + m12 + m13 + m15 using the K – map
method
90. Simplify the expression Y
=∑ 3, 4, 5, 7, 9, 13, 14, 15 , using the K –
map method.

4. Sanjay Ghodawat University
School of Technology
Department of Electronics Engineering
Dr. Nilesh Bhaskarrao Bahadure, SGU Page 4
91. Simplify the expression Y = Π (0,1, 4, 5, 6, 8, 9,
12, 13, 14) using the K – Map method.
92. Obtain (a) minimal sum of product and (b)
minimal product of sum expressions for the
function given below:
F (A, B, C, D) =∑ 0, 1, 2, 5, 8, 9, 10
93. Simplify
Y
=
∑ 3, 6, 7, 8, 10, 12, 14, 17, 19, 20, 21, 24, 25, 27, 28
using the K – Map Method.
94. Simplify the Boolean function
F (A, B, C, D) = ∑ 1, 3, 7, 11, 15
∑ 0, 2, 5
95. Using the K – Map method, simplify the
following Boolean function and obtain
(a) minimal SOP form
(b) minimal POS expression
Y = ∑ 0, 2, 3, 6, 7 ∑ 8, 10, 11, 15
96. Obtain the minimal SOP expression for the
function
𝑌
1, 5, 7, 13, 14, 15, 17, 18, 21, 22, 25, 29
6, 9, 19, 23, 30
97. Explain Quine Mc McClusky method, also
explain prime implicant chart.
98. Find the minimal sum of product for the
Boolean expression f =
∑ 1, 2, 3, 7, 8, 9, 10, 11, 14, 15 , using the
Quine Mc Clusky method
99. Find the minimal sum of product for the
Boolean expression , f(w, x, y, z) =
∑ 1, 3, 4, 5, 9, 10, 11 ∑ 6, 8 , using the
Quine McClusky method
100. Prepare K – Map for the following
functions
(a) F = ABC + A’BC + B’C’
(b) F = A + B + C’
(c) F = AB + B’CD
101. Using the K – Map method, obtain the
minimal sum of product expression of the
following function.
Y = ∑ 0, 2, 3, 6, 7, 8, 10, 11, 12, 15
102. Design BCD to Excess – 3 code
conversion. Simplify using K – map and show
the BCD to excess – 3 code design using logical
Gates.
103. Show the design of BCD to seven
segment decoder. Simplify using K map and
show the logical circuit using gates.
104. Design BCD – to Excess 3 code
converter using minimum number of NAND
gates.
105. Design Excess – 3 to BCD code
converter using minimum number of NAND
gates.
106. Design 4 bit binary to gray code
conversion and simplify using K map. Show
design using gates.
107. Show the design of 4 bit gray code to
4 bit binary conversion using digital logic
gates.
108. Explain the following with examples
(a) Weighted and non weighted codes.
(b) Reflective codes
(c) Sequential code
(d) Packed BCD and Unpacked BCD code
109. Write short notes on the following
(a) Error correcting codes.
(b) Error detecting codes.
(c) Single error correcting codes.
(d) Hamming codes
110. Differentiate between the K – map
simplification method and Quine McClusky
simplification method.
111. The 7’s complement of a certain octal
number is 5264. Determine the binary and
hexadecimal equivalent of that octal number

5. Dr.Nilesh B bahadure, School of Technology – Electronics Engineering, SGU Kolhapur 1
Question Bank
Subject: Digital Electronics & Circuits
Unit – III, IV, V and VI
Unit ‐ III
1. For a Boolean function f(A, B) = ∑ 0,2 prove
that f(A, B) = ∏ 1,3 and f’(A,B) = ∑ 1, 3
=∏ 0, 2
2. Simplify the Boolean expression using Quine –
McClusky method
A’BC + A’B’D + AC’D +BC’D’ + A’BC’D
3. Simplify the Boolean expression using Quine –
McClusky method
(A’+B’+C’+D’) (A’+B’+C’++D) (A’+B’+C+D’)
(A+B’+C’+D’) (A+B’+C+D’)
4. Using the Quine McClusky tabular method,
find the minimum sum of products for
f(A,B,C,D) = ∑ 1, 2, 3, 9, 12, 13, 14
∑ 0, 7, 10, 15
5. Minimize the Boolean function
F(A,B,C) = ∑ 0,1,3,5 ∑ 2,7
∅
Using the mapping method in both minimized
sum of product and product of sum forms.
6. A’B + CD is a simplified Boolean expression of
ABCD + A’B’CD + A’ B. Determine if there are
any don’t care entries.
7. Simplify the following Boolean expressions
(a) ABC + ABC’ + AB’ C+ AB’C’ + A’ BC + A’BC’
+ A’B’C’ + A’B’C
(b) (A’+B+C’) (A’ + B + C) (C + D) (C + D + E)
8. Find the dual of ABCD’ + AB’C’D+ A’B’C’D’
9. Find the complement of A + [(B + C’). D + E’]. F
10. The dual of the complement of the Boolean
expression is given by ABC + D’ E + B C’ E find
the expression.
11. Write minterm and maxterm Boolean
expression by f(ABC) = 𝛱 0, 3, 7
12. Write simplified maxterm Boolean expression
for 𝛱 0, 4, 5, 6, 7, 10, 14 using K – map
method.
13. Realize the logic function in SOP form using
Quine – McClusky method
F(A,B,C,D) = Π (2, 7, 8, 9, 10, 12)
14. Minimize the logic function using Quine‐
McClusky method F(ABCD) =
∑ 1, 3, 5, 8, 9, 11, 15 ∑ 2, 13
15. Minimize the logic function using Quine
McClusky method F(A,B,C,D,E) =
∑ 8, 9, 10, 11, 13, 15, 16, 18, 21, 24, 25, 26, 27, 30, 31
16. Simplify the following Boolean function using
Quine McClusky method
(a) f(A,B,C,D,E,F,G) =
∑ 20,21,28,29,52,53,60,61 ;
(b) f(A,B,C,D,E,F) =
6,9,13,18,19,25,26,27,29,41,45,57,61 .
UNIT ‐ IV
17. Design and explain the following in details
(a) Half adder
(b) Full adder
(c) Full adder using half adder
(d) Half subtractor
(e) Full Subtractor
(f) Full subtractor using half subtractor
18. Given the relevant Boolean expressions for
half‐adder and half‐subtractor circuits, design
a half‐Adder subtractor circuit that can be
used to perform either addition or subtraction
on two one‐bit numbers. The desired
arithmetic operation should be selectable
from a control input.
19. Design an 8 bit adder – subtractor circuit using
4 bit binary adder, type number 7483 and two
inputs Ex – OR gates, type number 7486.
20. Explain look ahead carry adder method in
details.
21. Explain four bit magnitude comparator. Also
write short notes on IC 7485
22. Design a two bit magnitude comparator. Also
write relevant Boolean expressions.
23. Explain parity generator and checker.
24. Implement Boolean function using
multiplexers f(A,B,C) = ∑ 2, 4, 7
(a) Design using 8:1 MUX
(b) Design using 4:1 MUX
25. Implement the product – of – sums Boolean
function expressed by Π 1, 2, 5 by a suitable
multiplexer.

6. Dr.Nilesh B bahadure, School of Technology – Electronics Engineering, SGU Kolhapur 2
26. Figure below shows the 8:1 MUX to
implement a certain four variable Boolean
function. From the given logic circuit
arrangement, derive the Boolean expression
implemented by the given circuit.
27. Explain multiplexer, demultiplexer, decoder
and encoder in details.
28. What is priority encoder explain in details.
29. Design a 4 line to 2 line priority encoder with
active high inputs and outputs, with priority
assigned to the higher order data input line.
30. Implement full adder circuit using
(a) 8:1 Multiplexer
(b) 4:1 Multiplexer
(c) 3 to 8 line decoder
31. A combinational circuit is defined by F =
∑ 0, 2, 5, 6, 7. Hardware implement the
Boolean function F with suitable decoder and
an external OR/NOR gate having the minimum
number of inputs.
32. Construct 4 to 16 line decoder with two 3 – 8
decoder having active low enable inputs.
33. Implement the three variable Boolean
function F (A,B,C) = A’ C + A B’ C + A B C’ using
(a) 8 : 1 MUX
(b) 4 : 1 MUX
34. Design a 32:1 MUX using 8:1 MUX having an
active low Enable input and a 2 to 4 decoder
35. Implement a full subtractor combinational
circuit using 3 to 8 decoder and an external
NOR gate.
36. Implement the expression using a multiplexer.
F(A, B, C, D) = ∑ 0,2,3,6,8,9,12,14 using
two methods.
37. Realize the logic function of the truth table
shown below using 8 : 1 MUX. Use variable D
as an input.
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
38. Implement 32:1 MUX using two 16:1 MUX and
one 2:1 MUX
39. Implement the following multi output
combinational logic circuit using a 4 to 16 line
decoder
F1= ∑ 1, 2, 4, 7, 8, 11, 12, 13
F2= ∑ 2, 3, 9, 11
F3= ∑ 10, 12, 13, 14
F4= ∑ 2, 4, 8
40. Realize the following functions of four variable
using
(a) 8 : 1 MUX
(b) 16: 1 MUX
(c) 4 to 16 line decoder with active low
outputs.
F1 = ∑ 0, 3, 5, 6, 9, 10, 12, 15
F2 = ∑ 0, 1, 2, 3, 11, 12, 14, 15
F3 = Π(0, 1, 3, 7, 9, 10, 11, 13, 14, 15)
41. Implement 5 line to 32 line decoder using two
4 line to 16 line decoders.
42. Implement 8 line to 256 line decoder using 4
line to 16 line decoder.
43. Explain and show the designs of
(a) BCD to decimal decoder / driver
(b) BCD to seven segment decoder
44. Explain and show the design of

7. Dr.Nilesh B bahadure, School of Technology – Electronics Engineering, SGU Kolhapur 3
(a) decimal to BCD encoder
(b) Octal to binary encoder
45. Design 40:1 MUX using 8:1 MUX
46. Design 1:40 DMUX using BCD to Decimal
decoder.
47. Implement 4:1 MUX suing three 2:1 MUX (No
gates)
48. Define PLA. Also explain programmable logic
array in details with suitable example.
49. Show the design of full adder using
programmable logic array.
50. Design a 4 input, 5 output combinational
circuit using PLA. The input variables are A, B,
C, and D.
Y1 = ∑ 0, 3, 5, 6, , 9, 10, 12, 15
Y2 = ∑ 0, 1, 2, 3, 11, 12, 14, 15
Y3 = ∑ 0, 4, 8, 12
Y4 = ∑ 0, 2, 3, 5, 7, 8, 12, 13
Y5 = ∑ 0, 1, 3, 4, 5, 6, 11, 13, 14, 15
UNIT – V and VI
51. Define latch? Also explain cross coupled
inverter used as a latch
52. Write short notes on
(a) S – R flip flop
(b) J – K flip flop
(c) T Flip flop
(d) D Flip flop
53. What is triggering in flip flop? Explain level
triggered and edge triggered activation in flip
flops.
54. What is master – slave flip flop, explain in
details.
55. What is meant by race around conditions in
the flip flop? , explain how to avoid it.
56. Design Delay flip flop using S – R flip flop.
57. Realize J – K flip flop using S – R flip flop
58. Construct T flip flop using S – R flip flop
59. Construct D flip flop using J – K flip flop
60. Explain shift registers in details.
61. Explain frequency division circuit using flip
flop. Also show the design circuit to divide the
input frequency by 4.
62. Define counters? Show three bit binary
counter using J – K flip flops.
63. Explain asynchronous and synchronous
counters with suitable example.
64. Define decade counter? Show the design of
decade counter.
65. Show the design of mod – 8 down counter.
66. Show the design of 4 bit UP/DOWN counter.
67. What is propagation delay is ripple counter,
explain in details.
68. Explain 4 bit parallel counter. Also explain the
differences between the ripple counter and
parallel counter.
69. Explain synchronous 4 – bit DOWN counter.
70. Show the design of synchronous UP/DOWN
counter with suitable example.
71. Show the design of mod – 3 counter.
72. Design mod – 6 counter in details.
73. Show the design of BCD or decade or mod –
10 counter.
74. Show the design of mod – 8 UP/DOWN
synchronous counter.
75. What is flip flop? Explain any three
applications of flip flop
76. Design the synchronous counter with the
following sequence
0000  0010 0100 0110 1000 1010
1100 1110 0000....
77. Design the synchronous counter with the
following sequence
0001  0011 0101 0111 1001
10111101 1111 0001....
78. What is shift registers, explain serial in parallel
out shift register.
79. What is universal shift register; explain
universal shift register in details.
80. Explain bidirectional shift registers in details.
81. The 100 kHz square waveform of Fig.1 (a) is
applied to the clock input of the flip‐flops
shown in Figs.1 (b) and (c). If the Q output is
initially 0, draw the Q output waveform in the
two cases. Also, determine the frequency of
the Q output in the two cases.

8. Dr.Nilesh B bahadure, School of Technology – Electronics Engineering, SGU Kolhapur 4
82.
83.