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Timing diagram of microprocessor 8085
The document provides a detailed overview of the timing diagram for the 8085 microprocessor, outlining various machine cycles, instruction groupings, and their respective execution times represented in t-states. It includes explanations of instruction cycles, machine cycles, and provides examples of specific instructions like conditional jumps and data transfer instructions. Additionally, the author illustrates how to draw timing diagrams for various 8085 instructions with practical examples.
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Timing diagram of microprocessor 8085
- 1. Timing Diagram ofMicroprocessor 8085 Dr. Nilesh Bhaskarrao Bahadure https://www.sites.google.com/site/nileshbbahadure/home July 26, 2021 Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 1 / 39
- 2. Overview I 1 Introductionto the Timing Diagram Introduction to the Timing Diagram Machine Cycles Machine Cycles of Microprocessor 8085 Opcode Fetch Machine Cycle Memory Read Machine Cycle Memory Write Machine Cycle IO Read Machine Cycle IO Write Machine Cycle 2 Group-I One Machine Cycle with 4 T - States 3 Group-II One Machine Cycle with 6 T - States 4 Group-III Two Machine Cycle Instructions Exceptions of the Group-III 5 Group-IV Three Machine Cycle Instructions 6 Group-V JMP Instruction Conditional Jump Instruction Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 2 / 39
- 3. Overview II 7 Group-VIRET Instruction Conditional RET Instruction 8 Group-VII CALL Instruction Conditional CALL Instruction 9 Group-VIII LDA STA LHLD SHLD XTHL Instruction 10 Examples Example-I MVI B, 43 Example-II INR M Example-III IN C0 Example-IV STA Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 3 / 39
- 4. Introduction to theTiming Diagram Timing Diagram is a graphical representation of the instruction execution in steps with respect to the time (clock signal). It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. The different types of cycles used in the timing diagram representation are as follows: Instruction Cycle: Instruction cycle is defined as the time required completing the execution of an instruction. The 8085 µP instruction cycle consists of one to five m/c cycles or one to five operations. Machine Cycle: Machine cycle is defined as the time required completing the operation of accessing memory or input / output. In 8085 µP, m/c cycle may consists of three to six timing state (T - state) Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 4 / 39
- 5. Introduction to theTiming Diagram... T-State: T State is defined as one subdivision of the operation performed in one clock period. These subdivisions are internal states synchronized with the system clock. Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 5 / 39
- 6. Machine Cycles Machine CycleStatus Signals Control Signals IO/M S1 S0 RD WR INTA Opcode Fetch 0 1 1 0 1 1 Memory Read 0 1 0 0 1 1 Memory Write 0 0 1 1 0 1 IO Read 1 1 0 0 1 1 IO Write 1 0 1 1 0 1 INTR ACK 1 1 1 1 1 0 Bus Idle 0 0 0 1 1 1 Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 6 / 39
- 7. Machine Cycles ofMicroprocessor 8085 Opcode fetch cycle (4T/6T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T) Halt state machine cycle Interrupt acknowledge machine cycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 7 / 39
- 8. Opcode Fetch MachineCycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 8 / 39
- 9. Memory Read MachineCycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 9 / 39
- 10. Memory Write MachineCycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 10 / 39
- 11. IO Read MachineCycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 11 / 39
- 12. IO Write MachineCycle Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 12 / 39
- 13. One Machine CycleInstructions 4 T - States Instruction Instruction Instruction MOV Rd, Rs XCHG ADD R ADC R SUB R SBB R RAL RLC RRC RAR STC CMC CMA INR R DCR R ANA R ORA R XRA R DAA EI DI SIM RIM NOP CMP R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 13 / 39
- 14. One Machine CycleInstructions 6 T - States Instruction Instruction INX Rp DCX Rp SPHL PCHL Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 14 / 39
- 15. Two Machine CycleInstructions Instruction Machine Cycle 1 Machine Cycle 2 MVI Rd, DATA F R MOV R,M F R MOV M,R F W ADI DATA F R ACI DATA F R SUI DATA F R SBI DATA F R ANI DATA F R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 15 / 39
- 16. Two Machine CycleInstructions... Instruction Machine Cycle 1 Machine Cycle 2 ORI DATA F R XRI DATA F R CPI DATA F R ADD M F R ADC M F R SUB M F R SBB M F R ANA M F R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 16 / 39
- 17. Two Machine CycleInstructions... Instruction Machine Cycle 1 Machine Cycle 2 ORA M F R XRA M F R CMP M M F R LDAX Rp F R STAX Rp F W Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 17 / 39
- 18. Exceptions of theGroup-III Instruction Instructions INR M DCR M MVI M, DATA IN 8-BIT PORT ADDRESS OUT 8-BIT PORT ADDRESS Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 18 / 39
- 19. Three Machine CycleInstructions Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3 LXI Rp, DATA F R R INR M F R W DCR M F R W MVI M, DATA F R W IN 8- bit Port Address F R I OUT 8- bit Port Address F R O PUSH Rp S W W POP Rp F R R RSTn S W W DAD Rp F B B Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 19 / 39
- 20. Conditional & UnconditionalJump Instructions Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3 JMP ADDR F R R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 20 / 39
- 21. Conditional Jump Instructions ConditionalBranching Instruction Condition not Satisfied Condition Satis- fied JC ADDR F R F R R JNC ADDR F R F R R JZ ADDR F R F R R JNZ ADDR F R F R R JP ADDR F R F R R JM ADDR F R F R R JPE ADDR F R F R R JPO ADDR F R F R R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 21 / 39
- 22. Conditional & UnconditionalRET Instructions Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3 RET F R R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 22 / 39
- 23. Conditional RET Instructions ConditionalBranching Instruction Condition not Satisfied Condition Satis- fied RC S S R R RNC S S R R RZ S S R R RNZ S S R R RP S S R R RM S S R R RPE S S R R RPO S S R R Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 23 / 39
- 24. Conditional & UnconditionalCALL Instructions Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3 m/c Cycle 4 m/c C 5 CALL ADDR S R R W W Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 24 / 39
- 25. Conditional CALL Instructions ConditionalBranching Instruction Condition not Satisfied Condition Satisfied CC ADDR S R S R R W W CNC ADDR S R S R R W W CZ ADDR S R S R R W W CNZ ADDR S R S R R W W CP ADDR S R S R R W W CM ADDR S R S R R W W CPE ADDR S R S R R W W CPO ADDR S R S R R W W Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 25 / 39
- 26. LDA STA LHLDSHLD XTHL Instruction Instruction Machine Cycles LDA ADDR F R R R STA ADDR F R R W LHLD ADDR F R R R R SHLD ADDR F R R W W XTHL F R R W W Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 26 / 39
- 27. Draw timing diagramfor MVI B, 43 Example Draw timing diagram for MVI B, 43H. Assume that instruction is located at memory location 2000h and the opcode of MVI B, data is 06h Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 27 / 39
- 28. Draw timing diagramfor MVI B, 43 Solution Address Mnemonics Opcode/Data 2000h MVI B, 43h 06h 2001h 43h Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 28 / 39
- 29. Draw timing diagramfor MVI B, 43 Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 29 / 39
- 30. Draw timing diagramfor INR M Example Draw timing diagram for the instruction INR M, which are located at memory location address 4105. Assume that the opcode of INR M is 34h, also assume that HL = 4250 and the contents of memory location 4250h is 12h. Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 30 / 39
- 31. Draw timing diagramfor INR M Solution Address Mnemonics Opcode/Data 4105h INR M 34h Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 31 / 39
- 32. Draw timing diagramfor INR M Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 32 / 39
- 33. Draw timing diagramfor IN C0 Example Draw the timing diagram for the instruction IN C0h with the following information 4125h DBh (Opcode of IN instruction) 4126h C0h Assume that the contents of the port address C0h is 5Eh Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 33 / 39
- 34. Draw timing diagramfor IN C0 Solution Address Mnemonics Opcode/Data 4125h IN C0h DBh 4126h C0h Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 34 / 39
- 35. Draw timing diagramfor IN C0 Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 35 / 39
- 36. Draw timing diagramfor STA 526Ah Example Draw the timing diagram for the STA 526A instruction, assume that the opcode of STA is 32h and it is fetched from the memory location address 41FFh. Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 36 / 39
- 37. Draw timing diagramfor STA 526Ah Solution Address Mnemonics Opcode/Data 41FFh STA 526Ah 32h 4200h 6Ah 4201h 52h Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 37 / 39
- 38. Draw timing diagramfor STA 526Ah Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 38 / 39
- 39. Thank you Please sendyour feedback at nbahadure@gmail.com For more details and updates kindly visit https://sites.google.com/site/nileshbbahadure/home Main Slide Dr. Nilesh Bhaskarrao Bahadure () Timing Diagram July 26, 2021 39 / 39