Total slides: 39 Introduction to the Timing Diagram Machine Cycles Machine Cycles of Microprocessor 8085 Opcode Fetch Machine Cycle Memory Read Machine Cycle Memory Write Machine Cycle IO Read Machine Cycle IO Write Machine Cycle Examples

1. Timing Diagram of Microprocessor 8085
Dr. Nilesh Bhaskarrao Bahadure
https://www.sites.google.com/site/nileshbbahadure/home
July 26, 2021
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2. Overview I
1 Introduction to the Timing Diagram
Introduction to the Timing Diagram
Machine Cycles
Machine Cycles of Microprocessor 8085
Opcode Fetch Machine Cycle
Memory Read Machine Cycle
Memory Write Machine Cycle
IO Read Machine Cycle
IO Write Machine Cycle
2 Group-I One Machine Cycle with 4 T - States
3 Group-II One Machine Cycle with 6 T - States
4 Group-III Two Machine Cycle Instructions
Exceptions of the Group-III
5 Group-IV Three Machine Cycle Instructions
6 Group-V JMP Instruction
Conditional Jump Instruction
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3. Overview II
7 Group-VI RET Instruction
Conditional RET Instruction
8 Group-VII CALL Instruction
Conditional CALL Instruction
9 Group-VIII LDA STA LHLD SHLD XTHL Instruction
10 Examples
Example-I MVI B, 43
Example-II INR M
Example-III IN C0
Example-IV STA
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4. Introduction to the Timing Diagram
Timing Diagram is a graphical representation of the instruction execution
in steps with respect to the time (clock signal). It represents the execution
time taken by each instruction in a graphical format. The execution time
is represented in T-states. The different types of cycles used in the timing
diagram representation are as follows:
Instruction Cycle:
Instruction cycle is defined as the time required completing the execution
of an instruction. The 8085 µP instruction cycle consists of one to five
m/c cycles or one to five operations.
Machine Cycle:
Machine cycle is defined as the time required completing the operation of
accessing memory or input / output. In 8085 µP, m/c cycle may consists
of three to six timing state (T - state)
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5. Introduction to the Timing Diagram...
T-State:
T State is defined as one subdivision of the operation performed in one
clock period. These subdivisions are internal states synchronized with the
system clock.
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6. Machine Cycles
Machine Cycle Status Signals Control Signals
IO/M S1 S0 RD WR INTA
Opcode Fetch 0 1 1 0 1 1
Memory Read 0 1 0 0 1 1
Memory Write 0 0 1 1 0 1
IO Read 1 1 0 0 1 1
IO Write 1 0 1 1 0 1
INTR ACK 1 1 1 1 1 0
Bus Idle 0 0 0 1 1 1
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7. Machine Cycles of Microprocessor 8085
Opcode fetch cycle (4T/6T)
Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)
Halt state machine cycle
Interrupt acknowledge machine cycle
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8. Opcode Fetch Machine Cycle
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9. Memory Read Machine Cycle
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10. Memory Write Machine Cycle
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11. IO Read Machine Cycle
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12. IO Write Machine Cycle
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13. One Machine Cycle Instructions 4 T - States
Instruction Instruction Instruction
MOV Rd, Rs XCHG ADD R
ADC R SUB R SBB R
RAL RLC RRC
RAR STC CMC
CMA INR R DCR R
ANA R ORA R XRA R
DAA EI DI
SIM RIM NOP
CMP R
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14. One Machine Cycle Instructions 6 T - States
Instruction Instruction
INX Rp DCX Rp
SPHL PCHL
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15. Two Machine Cycle Instructions
Instruction Machine
Cycle 1
Machine
Cycle 2
MVI Rd, DATA F R
MOV R,M F R
MOV M,R F W
ADI DATA F R
ACI DATA F R
SUI DATA F R
SBI DATA F R
ANI DATA F R
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16. Two Machine Cycle Instructions...
Instruction Machine
Cycle 1
Machine
Cycle 2
ORI DATA F R
XRI DATA F R
CPI DATA F R
ADD M F R
ADC M F R
SUB M F R
SBB M F R
ANA M F R
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17. Two Machine Cycle Instructions...
Instruction Machine
Cycle 1
Machine
Cycle 2
ORA M F R
XRA M F R
CMP M M F R
LDAX Rp F R
STAX Rp F W
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18. Exceptions of the Group-III
Instruction Instructions
INR M DCR M
MVI M, DATA IN 8-BIT PORT ADDRESS
OUT 8-BIT PORT ADDRESS
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19. Three Machine Cycle Instructions
Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3
LXI Rp, DATA F R R
INR M F R W
DCR M F R W
MVI M, DATA F R W
IN 8- bit Port Address F R I
OUT 8- bit Port Address F R O
PUSH Rp S W W
POP Rp F R R
RSTn S W W
DAD Rp F B B
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20. Conditional & Unconditional Jump Instructions
Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3
JMP ADDR F R R
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21. Conditional Jump Instructions
Conditional Branching
Instruction Condition not
Satisfied
Condition Satis-
fied
JC ADDR F R F R R
JNC ADDR F R F R R
JZ ADDR F R F R R
JNZ ADDR F R F R R
JP ADDR F R F R R
JM ADDR F R F R R
JPE ADDR F R F R R
JPO ADDR F R F R R
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22. Conditional & Unconditional RET Instructions
Instruction m/c Cycle 1 m/c Cycle 2 m/c Cycle 3
RET F R R
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23. Conditional RET Instructions
Conditional Branching
Instruction Condition not
Satisfied
Condition Satis-
fied
RC S S R R
RNC S S R R
RZ S S R R
RNZ S S R R
RP S S R R
RM S S R R
RPE S S R R
RPO S S R R
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24. Conditional & Unconditional CALL Instructions
Instruction m/c Cycle
1
m/c Cycle
2
m/c Cycle
3
m/c Cycle
4
m/c C
5
CALL
ADDR
S R R W W
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25. Conditional CALL Instructions
Conditional Branching
Instruction Condition not
Satisfied
Condition Satisfied
CC ADDR S R S R R W W
CNC ADDR S R S R R W W
CZ ADDR S R S R R W W
CNZ ADDR S R S R R W W
CP ADDR S R S R R W W
CM ADDR S R S R R W W
CPE ADDR S R S R R W W
CPO ADDR S R S R R W W
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26. LDA STA LHLD SHLD XTHL Instruction
Instruction Machine Cycles
LDA ADDR F R R R
STA ADDR F R R W
LHLD ADDR F R R R R
SHLD ADDR F R R W W
XTHL F R R W W
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27. Draw timing diagram for MVI B, 43
Example
Draw timing diagram for MVI B, 43H. Assume that instruction is located
at memory location 2000h and the opcode of MVI B, data is 06h
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28. Draw timing diagram for MVI B, 43
Solution
Address Mnemonics Opcode/Data
2000h MVI B, 43h 06h
2001h 43h
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29. Draw timing diagram for MVI B, 43
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30. Draw timing diagram for INR M
Example
Draw timing diagram for the instruction INR M, which are located at
memory location address 4105. Assume that the opcode of INR M is 34h,
also assume that HL = 4250 and the contents of memory location 4250h
is 12h.
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31. Draw timing diagram for INR M
Solution
Address Mnemonics Opcode/Data
4105h INR M 34h
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32. Draw timing diagram for INR M
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33. Draw timing diagram for IN C0
Example
Draw the timing diagram for the instruction IN C0h with the following
information
4125h DBh (Opcode of IN instruction)
4126h C0h
Assume that the contents of the port address C0h is 5Eh
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34. Draw timing diagram for IN C0
Solution
Address Mnemonics Opcode/Data
4125h IN C0h DBh
4126h C0h
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35. Draw timing diagram for IN C0
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36. Draw timing diagram for STA 526Ah
Example
Draw the timing diagram for the STA 526A instruction, assume that the
opcode of STA is 32h and it is fetched from the memory location address
41FFh.
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37. Draw timing diagram for STA 526Ah
Solution
Address Mnemonics Opcode/Data
41FFh STA 526Ah 32h
4200h 6Ah
4201h 52h
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38. Draw timing diagram for STA 526Ah
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39. Thank you
Please send your feedback at nbahadure@gmail.com
For more details and updates kindly visit
https://sites.google.com/site/nileshbbahadure/home
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