Interrupts of microprocessor 8085

Interrupts of 8085 Microprocessor
Dr. Nilesh Bhaskarrao Bahadure
https://www.sites.google.com/site/nileshbbahadure/home
July 26, 2021
Dr. Nilesh Bhaskarrao Bahadure () Unit - IV (Part - I) July 26, 2021 1 / 36

Overview I
1 Syllabus
2 Introduction to Interrupts
Introduction to Interrupts
What happen when interrupt is occurs
3 Interrupt Vs Polling
4 Classification of Interrupts
Hardware Interrupts of 8085
Software Interrupts of 8085
Maskable Interrupts of Microprocessor 8085
Non - Maskable Interrupts of Microprocessor 8085
Vectored Interrupts of Microprocessor 8085
Non - Vectored Interrupts of Microprocessor 8085
5 8085 Microprocessor Interrupt Structure
Interrupt Structure of Microprocessor 8085
6 SIM Instruction
Example on SIM Instruction

Overview II
7 Non - Vectored Interrupt
Restart sequence
8 Pending Interrupts
RIM Instruction
9 Multiple Interrupts
10 Thank You

Outline of Interrupts
Main Slide

Introduction to Interrupts
Interrupt is a process where an external device can get the attention of the
microprocessor.
1. The process starts from the I/O device
2. The process is asynchronous.
An interrupt is considered to be an emergency signal that may be serviced.
The Microprocessor may respond to it as soon as possible.
Interrupt is signals send by an external device to the processor, to request
the processor to perform a particular task or work. Mainly in the
microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor. The processor will check
the interrupts always at the 2nd T-state of last machine cycle. If there is
any interrupt it accept the interrupt and send the INTA (active low) signal
to the peripheral
Main Slide

What happen when interrupt is occurs
1 When the Microprocessor receives an interrupt signal, it suspends the
currently executing program and jumps to an Interrupt Service
Routine (ISR) to respond to the incoming interrupt.
2 Each interrupt will most probably have its own ISR.
Main Slide

What happen when interrupt is occurs...
Figure : Interrupt Process
Main Slide

Interrupt Vs Polling
A single microprocessor can serve several devices. There are two ways to
do that: Interrupts and polling.
Interrupts:
In the interrupt method, whenever any device needs its service, the device
notifies the microprocessor by sending an interrupt signal, upon receiving
an interrupt signal, the microprocessor interrupts whatever it is doing and
serve the device. The program associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
Main Slide

Interrupt Vs Polling...
Polling:
In polling, the microprocessor continuously monitors the status of a several
devices, when the status condition is met, it perform the service, after that,
it moves on to monitor the next device until each one is serviced. Although
polling can monitors the status of several devices and serve each of them
as certain conditions are met, it is not an efficient use of microprocessor.
Main Slide

Interrupt Vs Polling...
Figure : Polling method to access several devices
Main Slide

Classification of Interrupts
Interrupts are mainly classified into different types as follows:
1 Hardware interrupts
2 Software interrupts
3 Maskable interrupts
4 Non - maskable interrupts
5 Vectored interrupts
6 Non - vectored interrupts
Main Slide

Hardware Interrupts of 8085
An external device initiates the hardware interrupts and placing an appropri-
ate signal at the interrupt pin of the processor. If the interrupt is accepted
then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
TRAP RST 7.5 RST 6.5 RST 5.5 INTR
Main Slide

Software Interrupts of 8085
The software interrupts are program instructions. These instructions are
inserted at desired locations in a program. Software interrupt are special
instructions supported by microprocessor. After executing of these instruc-
tions microprocessor completes the execution of the current machine cycle
or current operation and then transfers the program control to the subrou-
tine program. Upon completion of the execution of the subroutine program,
program control returns back to the main program from where the micro-
processor has left previously.
The 8085 has eight software interrupts from RST 0 to RST 7. The vector
address for software interrupt RST0 to RST7 can be calculated as follows
Interrupt number * 8 = vector location address
Main Slide

Maskable Interrupts of Microprocessor 8085
Maskable interrupts are enabled and disabled under program control. By
setting or resetting particular flip flop in the microprocessor, interrupts can
be masked or unmasked respectively. When masked, microprocessor does
not respond to the interrupt even through the interrupt is activated.
Main Slide

In the microprocessor those interrupt which can be masked under software
control are called maskable interrupt whereas the interrupt which cannot
be masked under software control are called unmaskable or non maskable
interrupt. These types of interrupt are specially used in the emergency
shutoff.
Main Slide

Figure : Representation of Maskable and Non - Maskable Interrupts
Main Slide

Vectored Interrupts of Microprocessor 8085
When interrupt signal is activated, the internal control circuit of micropro-
cessor produces a CALL to a predetermined memory location. This memory
location, where the subroutine i.e. interrupts service routine (ISR) starts is
referred to as vector location and such interrupts are called vectored inter-
rupts.
Main Slide

Non - Vectored Interrupts of Microprocessor 8085
In response to the interrupt signal, the interrupt service routine address is not
defined by CALL or not produced CALL by microprocessor internally then
it is referred as non vectored interrupt. In this type of interrupt, interrupt
service routine address is generate using external hardware circuitry (buffer,
decoder or encoder etc).
Main Slide

Interrupt Structure of Microprocessor 8085
Figure : Interrupt Structure of Microprocessor 8085
Main Slide

Interrupt Structure of Microprocessor 8085...
Interrupt
Name
Maskable Masking
Method
Vectored Vector
location
Memory Triggering
Method
Priority
INTR
Yes
DI/EI
No – No
Level
Sensi-
tive
5 (Lowest)
RST
5.5
Yes
DI/EI
SIM
Yes
002Ch
No
Level
Sensi-
tive
4
RST
6.5
Yes
DI/EI
SIM
Yes
0034h
No
Level
Sensi-
tive
3
RST
7.5
Yes
DI/EI
SIM
Yes
003Ch
Yes
Edge
Sensi-
tive
2
TRAP
No
None
Yes
0024h
No Level
Edge
Sensi-
tive
1 (Highest)
Table : hardware Interrupts of Microprocessor 8085

SIM Instruction
Figure : SIM Instruction
Main Slide

Example - 1
Example - 1
Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and
RST7.5 is enabled.
Solution
EI ; Enable interrupts including INTR
MVI A, 0Ah ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
Main Slide

Non - Vectored Interrupt I
Example
Explain non-vectored interrupt. Also explain how to generate vector
location for non-vectored interrupt
1 The interrupt process should be enabled using the EI instruction.
2 The 8085 checks for an interrupt during the execution of every
instruction.
3 If INTR is high, MP completes current instruction, disables the
interrupt and sends INTA (Interrupt acknowledge) signal to the device
that interrupted .
4 INTA allows the I/O device to send a RST instruction through data
bus.

Non - Vectored Interrupt II
5 Upon receiving the INTA signal, MP saves the memory location of
the next instruction on the stack and the program is transferred to
call location (ISR Call) specified by the RST instruction.
6 Microprocessor Performs the ISR.
7 ISR must include the EI instruction to enable the further interrupt
within the program.
8 RET instruction at the end of the ISR allows the MP to retrieve the
return address from the stack and the program is transferred back to
where the program was interrupted.
9 Although INTR is a maskable interrupt, it does NOT need SIM to get
enabled.
Just instruction EI is enough.
The 8085 recognizes 8 RESTART instructions: RST0 - RST7.
Each of these would send the execution to a predetermined hard-wired
memory location:

Non - Vectored Interrupt III
Restart instruction Equivalent to
RST 0 CALL 0000H
RST 1 CALL 0008H
RST 2 CALL 0010H
RST 3 CALL 0018H
RST 4 CALL 0020H
RST 5 CALL 0028H
RST 6 CALL 0030H
RST 7 CALL 0038H
Main Slide

Restart Sequence
1 The restart sequence is made up of three machine cycles
2 In the 1st machine cycle:The Microprocessor sends the INTA signal.
3 While INTA is active the microprocessor reads the data lines
expecting to receive, from the interrupting device, the opcode for the
specific RST instruction.
4 In the 2nd and 3rd machine cycles:the 16-bit address of the next
instruction is saved on the stack.
5 Then the microprocessor jumps to the address associated with the
specified RST instruction.
6 There are 8 different RST instructions.
7 Each RST instruction tells the processor to go to a specific memory
address (call location fixed)
Main Slide

Restart Sequence...
Reading the RST 5 instruction
The above example is for generating RST 5:
RST 5’s opcode is EF =11101111 Main Slide

Restart Sequence...
During the interrupt acknowledge machine cycle, (the 1st machine cycle of
the RST operation):
1 The Microprocessor activates the INTA signal.
2 This signal will enable the Tri-state buffers, which will place the value
EFH on the data bus.
3 Therefore, sending the Microprocessor the RST 5 instruction.
The RST 5 instruction is exactly equivalent to CALL 0028H
Main Slide

Pending Interrupts
1 Since the 8085 has five interrupt lines, interrupts may occur during an
ISR and remain pending.
2 Using the RIM instruction, it is possible to can read the status of the
interrupt lines and find if there are any pending interrupts
Main Slide

RIM Instruction
Load the accumulator with an 8-bit pattern showing the status of each
interrupt pin and mask.
Main Slide

RIM Instruction...
Main Slide

RIM Instruction...
1 Bits 0-2 show the current setting of the mask for each of RST 7.5,
RST 6.5 and RST 5.5 .They return the contents of the three mask
flip flops.
2 Bit 3 shows whether the maskable interrupt process is enabled or not.
It can be used by a program to determine whether or not interrupts
are enabled.
3 Bits 4-6 show whether or not there are pending interrupts on RST
7.5, RST 6.5, and RST 5.5 .
4 Bit 7 is used for Serial Data Input.
The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit.
Main Slide

Multiple Interrupts
1 Microprocessor can be interrupted again before the completion of the
ISR.
2 As soon as the 1st interrupt arrives, all maskable interrupts are
disabled.
3 They will only be enabled after the execution of the EI instruction.
4 If the EI instruction is placed early in the ISR, other interrupt may
occur before the ISR is done.

Multiple Interrupts...
There are 8 different RST Instructions
Multiple interrupts coming from 8 different external devices
Main Slide

Multiple Interrupts...
1 How do MPU allow multiple devices to interrupt using the INTR line?
2 The microprocessor can only respond to one signal on INTR at a time.
3 Therefore, we must allow the signal from only one of the devices to
reach the microprocessor.
4 We must assign some priority to the different devices and allow their
signals to reach the microprocessor according to the priority.
Main Slide

Thank you
Please send your feedback at nbahadure@gmail.com
For more details and updates kindly visit
https://sites.google.com/site/nileshbbahadure/home
Main Slide

Interrupts of microprocessor 8085

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