The document provides an agenda and overview for a seminar on FPGA and CPLD technologies as well as VHDL programming basics. The seminar schedule covers topics such as FPGA technologies compared to previous programmable devices, the current FPGA scenario and a specific ACTEL FPGA family, and an introduction to VHDL programming. It also includes an application example of using an FPGA for an Ethernet bus interface board. Other sections provide more details on comparing FPGA and CPLD architectures and configurations, and a history of the evolution of programmable logic technologies.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
This document discusses complex programmable logic devices (CPLDs). CPLDs contain multiple simpler programmable logic devices (SPLDs) like PALs or GALs on a single chip connected by a programmable interconnect. This allows CPLDs to implement larger logic functions than SPLDs. CPLDs are made up of logic blocks, input/output blocks, and a programmable interconnect that can connect any logic block inputs or outputs. CPLDs generally provide better performance and more predictable timing than FPGAs but have lower density.
The document discusses an agenda covering field-programmable logic devices (FPLDs) including complex programmable logic devices (CPLDs). It provides an overview of CPLD architecture, describing them as composed of multiple simpler programmable logic devices (SPLDs) like PALs interconnected on a single chip. It also discusses CPLD vendors and families, noting they provide devices with differing numbers of logic blocks and I/O pins depending on the intended application.
The document describes the Xilinx Virtex 7 FPGA. It discusses the FPGA's key capabilities including its high logic density enabled by stacked silicon interconnect technology, which allows multiple FPGA dies on a single interposer. This provides high bandwidth connectivity between super logic regions with low latency and power consumption. The Virtex 7 FPGA addresses market needs for lower power consumption and higher performance. It offers benefits over ASICs such as rapid prototyping and reprogrammability. Applications include ASIC prototyping, communication systems, and high performance computing.
This document discusses CPLDs (Complex Programmable Logic Devices), including their general architecture, reprogrammability, density, and common vendors and families. CPLDs contain programmable macrocells (equivalent to around 20 gates each) connected by a programmable interconnect and support up to 200 I/O pins. They are between FPGAs and SPLDs in complexity. The document describes CPLD architecture including logic array blocks (LABs) and programmable interconnect arrays (PIAs). It provides examples of Xilinx CPLD families, packages, and a datasheet for the XC9572 device.
The document discusses three types of programmable logic devices (FPLDs): simple PLDs (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). SPLDs contain less than 1000 logic gates, CPLDs have higher logic capacity than SPLDs, and FPGAs have the highest logic capacity. CPLDs are composed of multiple SPLDs like PALs interconnected on a single chip, allowing for larger designs than SPLDs.
Digitronix Nepal presented on electronics hardware design using field programmable gate arrays (FPGAs). They discussed FPGA technology, applications, opportunities, and trends globally and nationally. Engineering colleges in Nepal are incorporating FPGA courses and some have established FPGA research and development centers with support from Digitronix Nepal. National activities have included FPGA design contests and trainings to promote use of FPGAs in academic projects.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
This document discusses complex programmable logic devices (CPLDs). CPLDs contain multiple simpler programmable logic devices (SPLDs) like PALs or GALs on a single chip connected by a programmable interconnect. This allows CPLDs to implement larger logic functions than SPLDs. CPLDs are made up of logic blocks, input/output blocks, and a programmable interconnect that can connect any logic block inputs or outputs. CPLDs generally provide better performance and more predictable timing than FPGAs but have lower density.
The document discusses an agenda covering field-programmable logic devices (FPLDs) including complex programmable logic devices (CPLDs). It provides an overview of CPLD architecture, describing them as composed of multiple simpler programmable logic devices (SPLDs) like PALs interconnected on a single chip. It also discusses CPLD vendors and families, noting they provide devices with differing numbers of logic blocks and I/O pins depending on the intended application.
The document describes the Xilinx Virtex 7 FPGA. It discusses the FPGA's key capabilities including its high logic density enabled by stacked silicon interconnect technology, which allows multiple FPGA dies on a single interposer. This provides high bandwidth connectivity between super logic regions with low latency and power consumption. The Virtex 7 FPGA addresses market needs for lower power consumption and higher performance. It offers benefits over ASICs such as rapid prototyping and reprogrammability. Applications include ASIC prototyping, communication systems, and high performance computing.
This document discusses CPLDs (Complex Programmable Logic Devices), including their general architecture, reprogrammability, density, and common vendors and families. CPLDs contain programmable macrocells (equivalent to around 20 gates each) connected by a programmable interconnect and support up to 200 I/O pins. They are between FPGAs and SPLDs in complexity. The document describes CPLD architecture including logic array blocks (LABs) and programmable interconnect arrays (PIAs). It provides examples of Xilinx CPLD families, packages, and a datasheet for the XC9572 device.
The document discusses three types of programmable logic devices (FPLDs): simple PLDs (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). SPLDs contain less than 1000 logic gates, CPLDs have higher logic capacity than SPLDs, and FPGAs have the highest logic capacity. CPLDs are composed of multiple SPLDs like PALs interconnected on a single chip, allowing for larger designs than SPLDs.
Digitronix Nepal presented on electronics hardware design using field programmable gate arrays (FPGAs). They discussed FPGA technology, applications, opportunities, and trends globally and nationally. Engineering colleges in Nepal are incorporating FPGA courses and some have established FPGA research and development centers with support from Digitronix Nepal. National activities have included FPGA design contests and trainings to promote use of FPGAs in academic projects.
Digital VLSI Design and FPGA ImplementationAmber Bhaumik
This document provides an overview of digital VLSI design and FPGA implementation training. The objective of the training is to provide exposure to VLSI engineering concepts and design methodologies relevant to industry needs. The training covers VLSI fundamentals, digital design, VHDL, FPGA implementation, and includes hands-on labs. Students will learn to design digital circuits using VHDL and will simulate and implement designs on FPGAs. After completing the training, students will be able to design any digital circuit using VHDL.
The document discusses different types of field-programmable logic devices (FPLDs) including simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). It provides an overview of CPLDs, describing their basic architecture and how they expanded on SPLD technology by incorporating multiple SPLDs onto a single chip with programmable interconnect. Examples of vendor CPLD devices like the Xilinx XC9500 series are also mentioned.
The document discusses different types of application specific integrated circuits (ASICs). It describes ASICs as integrated circuits customized for a particular application, as opposed to standard integrated circuits. The document outlines two main types of ASICs: full-custom ASICs which have all logic cells and mask layers customized, and semi-custom ASICs which use pre-designed logic cells but have customized mask layers. Within semi-custom ASICs it distinguishes between standard cell-based and gate array-based designs. The document also covers programmable ASICs including PLDs, CPLDs and FPGAs.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
The document discusses the architecture and programming of CPLDs and FPGAs. CPLDs and FPGAs are types of programmable logic devices (PLDs) that can implement complex digital logic functions. CPLDs contain logic blocks that can be programmed, while FPGAs contain an array of configurable logic blocks and interconnects. The document describes the components and programming of PLDs like PLA and PAL, as well as the logic cells and interconnects that make up CPLDs and FPGAs.
TRACK F: OpenCL for ALTERA FPGAs, Accelerating performance and design product...chiportal
The document discusses OpenCL for accelerating FPGA designs. It provides an overview of technology trends favoring parallelism and programmability. OpenCL is presented as a solution to bring FPGA design closer to software development by providing a standard programming model and faster compilation. The document describes how OpenCL maps to FPGAs by compiling kernels to hardware pipelines and discusses examples accelerated using OpenCL on FPGAs, including AES encryption, option pricing, document filtering, and video compression.
This document provides an overview of an ASIC/FPGA technology and design flow course. It discusses the course organization, material, schedule, and recommended literature. The course will cover FPGA and ASIC design flows, including Verilog, synthesis, simulation, and implementation. It will also discuss chip structures, technologies, applications and the semiconductor industry. Students will complete projects to design an FPGA peripheral and an ASIC, with design reviews to mimic industry practice. The goal is to prepare students for careers in chip design and verification.
The FPGA design flow document outlines the typical steps for designing an FPGA including: 1) specification and system-level simulation, 2) device selection between Xilinx and Altera, 3) design entry using languages like Verilog and VHDL, 4) functional simulation, 5) synthesis, 6) placement and routing (P&R), 7) timing simulation, and 8) programming and debugging the final design on hardware.
The document provides a history of digital logic and programmable logic devices such as PLDs, CPLDs, and ASICs. It describes the advantages of FPGAs over other technologies including lower costs, faster time to market, and easier design changes. The architecture of FPGAs is explained including logic blocks, interconnects, embedded memory and DSP blocks. Modern SoC FPGAs integrate an ARM processor for improved performance. Applications include automotive, wireless, military, and medical imaging systems.
Renjini has over 8 years of experience in FPGA and ASIC design using VHDL and Verilog. She has expertise in digital design, processor architectures, and validation of FPGA boards. Some of her projects include designing FIR filters, USB specifications, and integrating peripherals into an SoC. She is skilled in languages like VHDL, Verilog, and C. Renjini holds an MTech in VLSI design and has worked on telecom products at Cyient and Tech Mahindra.
FPGA BASED VLSI DESIGN
FPGAs allow designers to emulate IC designs using programming languages like VHDL and Verilog before final hardware implementation. FPGAs contain programmable logic blocks and interconnects that can be configured to implement different digital circuits. Common FPGA architectures include a 2D array of configurable logic blocks and routing channels that can be programmed to connect logic blocks according to a design. FPGAs offer advantages like reprogrammability, fast development times, and performance gains for software applications.
Application specific integrated circuits (ASICs) are microchips designed for special applications. There are two types: full-custom ASICs where all logic cells and mask layers are customized, and semi-custom where pre-designed logic cells have some customizable mask layers. ASICs have advantages over FPGAs like lower costs, higher speeds, and lower power usage, but have higher design costs and longer development times. Common applications of ASICs include aerospace systems, high-performance processors, and specialized consumer electronics.
"Field Programmable Gate Array (FPGA)" devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FPGA Selection Methodology for Real time projectsKrishna Gaihre
- The document discusses various factors to consider when selecting an FPGA chip for a project, such as resource utilization, IO count, frequency, power, cost, package size, available IP cores, vendor support, and EDA tool support.
- It outlines the FPGA offerings from major vendors Xilinx and Altera/Intel, including families like Zynq, Artix, Virtex, Stratix and Cyclone that are suitable for different applications and performance levels.
- Key trends in the FPGA market include growing use in embedded systems, computer vision, high-speed networks, and other domains, with devices integrating both programmable logic and processor systems.
Implementation of Soft-core processor on FPGA (Final Presentation)Deepak Kumar
Implementation of Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
FPGA stands for field programmable gate array. FPGAs contain configurable logic blocks that can be connected through connection bars and modified for various applications. FPGAs have different features than ASICs and can be specified using HDL scripts similarly to ASICs. FPGAs provide advantages over ASICs such as shorter design time and lower costs.
The document discusses a project to implement a secure RFID system using FPGA and a microcontroller. The project members are Sahil Sood, Anshul Gupta, and Paras Thakur, guided by Mr. Dheeraj Kumar. The proposed system aims to address privacy and security issues in RFID systems like traceability. It will use a hardware implementation of an RFID tag with a secure mutual authentication protocol between the tag and reader. The system will be simulated using ISE simulator and synthesized using Xilinx tools before being implemented on FPGA and microcontroller hardware.
The document discusses convolution and its applications in digital signal processing. It begins with an introduction to convolution and its mathematical definitions for both continuous and discrete time signals. It then discusses various types of convolution including linear and circular convolution. The properties of convolution such as commutativity, associativity and distributivity are also covered. Applications of convolution in areas such as statistics, optics, acoustics, electrical engineering and digital signal processing are summarized. Finally, the document discusses symmetric convolution and its advantages over traditional convolution methods.
This document describes the features of Quant Studio, software for advanced charting and technical analysis. It provides tools for creating charts with different types of data, applying studies and indicators, and customizing visual settings. Users can view charts in real-time or historical modes, change the time period displayed, and overlay studies like moving averages. The software includes a library of over 100 technical indicators and allows editing properties and styles.
Digital VLSI Design and FPGA ImplementationAmber Bhaumik
This document provides an overview of digital VLSI design and FPGA implementation training. The objective of the training is to provide exposure to VLSI engineering concepts and design methodologies relevant to industry needs. The training covers VLSI fundamentals, digital design, VHDL, FPGA implementation, and includes hands-on labs. Students will learn to design digital circuits using VHDL and will simulate and implement designs on FPGAs. After completing the training, students will be able to design any digital circuit using VHDL.
The document discusses different types of field-programmable logic devices (FPLDs) including simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). It provides an overview of CPLDs, describing their basic architecture and how they expanded on SPLD technology by incorporating multiple SPLDs onto a single chip with programmable interconnect. Examples of vendor CPLD devices like the Xilinx XC9500 series are also mentioned.
The document discusses different types of application specific integrated circuits (ASICs). It describes ASICs as integrated circuits customized for a particular application, as opposed to standard integrated circuits. The document outlines two main types of ASICs: full-custom ASICs which have all logic cells and mask layers customized, and semi-custom ASICs which use pre-designed logic cells but have customized mask layers. Within semi-custom ASICs it distinguishes between standard cell-based and gate array-based designs. The document also covers programmable ASICs including PLDs, CPLDs and FPGAs.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
The document discusses the architecture and programming of CPLDs and FPGAs. CPLDs and FPGAs are types of programmable logic devices (PLDs) that can implement complex digital logic functions. CPLDs contain logic blocks that can be programmed, while FPGAs contain an array of configurable logic blocks and interconnects. The document describes the components and programming of PLDs like PLA and PAL, as well as the logic cells and interconnects that make up CPLDs and FPGAs.
TRACK F: OpenCL for ALTERA FPGAs, Accelerating performance and design product...chiportal
The document discusses OpenCL for accelerating FPGA designs. It provides an overview of technology trends favoring parallelism and programmability. OpenCL is presented as a solution to bring FPGA design closer to software development by providing a standard programming model and faster compilation. The document describes how OpenCL maps to FPGAs by compiling kernels to hardware pipelines and discusses examples accelerated using OpenCL on FPGAs, including AES encryption, option pricing, document filtering, and video compression.
This document provides an overview of an ASIC/FPGA technology and design flow course. It discusses the course organization, material, schedule, and recommended literature. The course will cover FPGA and ASIC design flows, including Verilog, synthesis, simulation, and implementation. It will also discuss chip structures, technologies, applications and the semiconductor industry. Students will complete projects to design an FPGA peripheral and an ASIC, with design reviews to mimic industry practice. The goal is to prepare students for careers in chip design and verification.
The FPGA design flow document outlines the typical steps for designing an FPGA including: 1) specification and system-level simulation, 2) device selection between Xilinx and Altera, 3) design entry using languages like Verilog and VHDL, 4) functional simulation, 5) synthesis, 6) placement and routing (P&R), 7) timing simulation, and 8) programming and debugging the final design on hardware.
The document provides a history of digital logic and programmable logic devices such as PLDs, CPLDs, and ASICs. It describes the advantages of FPGAs over other technologies including lower costs, faster time to market, and easier design changes. The architecture of FPGAs is explained including logic blocks, interconnects, embedded memory and DSP blocks. Modern SoC FPGAs integrate an ARM processor for improved performance. Applications include automotive, wireless, military, and medical imaging systems.
Renjini has over 8 years of experience in FPGA and ASIC design using VHDL and Verilog. She has expertise in digital design, processor architectures, and validation of FPGA boards. Some of her projects include designing FIR filters, USB specifications, and integrating peripherals into an SoC. She is skilled in languages like VHDL, Verilog, and C. Renjini holds an MTech in VLSI design and has worked on telecom products at Cyient and Tech Mahindra.
FPGA BASED VLSI DESIGN
FPGAs allow designers to emulate IC designs using programming languages like VHDL and Verilog before final hardware implementation. FPGAs contain programmable logic blocks and interconnects that can be configured to implement different digital circuits. Common FPGA architectures include a 2D array of configurable logic blocks and routing channels that can be programmed to connect logic blocks according to a design. FPGAs offer advantages like reprogrammability, fast development times, and performance gains for software applications.
Application specific integrated circuits (ASICs) are microchips designed for special applications. There are two types: full-custom ASICs where all logic cells and mask layers are customized, and semi-custom where pre-designed logic cells have some customizable mask layers. ASICs have advantages over FPGAs like lower costs, higher speeds, and lower power usage, but have higher design costs and longer development times. Common applications of ASICs include aerospace systems, high-performance processors, and specialized consumer electronics.
"Field Programmable Gate Array (FPGA)" devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FPGA Selection Methodology for Real time projectsKrishna Gaihre
- The document discusses various factors to consider when selecting an FPGA chip for a project, such as resource utilization, IO count, frequency, power, cost, package size, available IP cores, vendor support, and EDA tool support.
- It outlines the FPGA offerings from major vendors Xilinx and Altera/Intel, including families like Zynq, Artix, Virtex, Stratix and Cyclone that are suitable for different applications and performance levels.
- Key trends in the FPGA market include growing use in embedded systems, computer vision, high-speed networks, and other domains, with devices integrating both programmable logic and processor systems.
Implementation of Soft-core processor on FPGA (Final Presentation)Deepak Kumar
Implementation of Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
FPGA stands for field programmable gate array. FPGAs contain configurable logic blocks that can be connected through connection bars and modified for various applications. FPGAs have different features than ASICs and can be specified using HDL scripts similarly to ASICs. FPGAs provide advantages over ASICs such as shorter design time and lower costs.
The document discusses a project to implement a secure RFID system using FPGA and a microcontroller. The project members are Sahil Sood, Anshul Gupta, and Paras Thakur, guided by Mr. Dheeraj Kumar. The proposed system aims to address privacy and security issues in RFID systems like traceability. It will use a hardware implementation of an RFID tag with a secure mutual authentication protocol between the tag and reader. The system will be simulated using ISE simulator and synthesized using Xilinx tools before being implemented on FPGA and microcontroller hardware.
The document discusses convolution and its applications in digital signal processing. It begins with an introduction to convolution and its mathematical definitions for both continuous and discrete time signals. It then discusses various types of convolution including linear and circular convolution. The properties of convolution such as commutativity, associativity and distributivity are also covered. Applications of convolution in areas such as statistics, optics, acoustics, electrical engineering and digital signal processing are summarized. Finally, the document discusses symmetric convolution and its advantages over traditional convolution methods.
This document describes the features of Quant Studio, software for advanced charting and technical analysis. It provides tools for creating charts with different types of data, applying studies and indicators, and customizing visual settings. Users can view charts in real-time or historical modes, change the time period displayed, and overlay studies like moving averages. The software includes a library of over 100 technical indicators and allows editing properties and styles.
FPGA stands for field programmable gate array. It consists of configurable logic blocks, programmable interconnects, and I/O blocks. The configurable logic blocks contain look up tables, flip flops, and multiplexers that can be programmed to implement different logic functions. The programmable interconnects allow connections between logic blocks using switch matrices. I/O blocks interface signals with the external world. FPGAs can be programmed by defining behavior in HDL, generating a netlist, performing validation, and configuring the FPGA with a binary file via JTAG. They are used in applications like DSPs, medical imaging, and ASIC prototyping. Advantages include shorter time to market and re
This document discusses FPGA configuration, including:
1. The FPGA configuration process involves clearing memory, initialization, loading configuration data, and startup.
2. Configuration modes like master serial, slave serial, and daisy chaining allow loading data from external sources.
3. Daisy chaining connects the configuration pins of multiple FPGAs together to load design data into all devices from a single source.
This document discusses configurable logic devices (CLDs) and field programmable gate arrays (FPGAs). It describes the structure of a CPLD as consisting of logic blocks with macrocells and programmable interconnects. An FPGA consists of an array of configurable logic blocks surrounded by programmable I/O blocks and connected with programmable interconnects. The document provides details on the architecture and components of Xilinx XC9500 CPLDs and the configuration of logic blocks, look-up tables, flip-flops, and programmable interconnects in FPGAs.
The document discusses FPGA architecture and programming technologies. It provides an overview of FPGA components like logic blocks and interconnect frameworks. It compares SRAM, anti-fuse, EPROM and EEPROM programming technologies in FPGAs and how each is configured and reprogrammed. Commercially available FPGAs from Xilinx and CPLDs from Altera are described as examples.
This document discusses the programming technologies and interconnect architectures used in different FPGA devices. It covers antifuse-based OTP technologies used in Actel FPGAs, SRAM-based reprogrammable technologies used in Xilinx FPGAs, and EPROM/EEPROM technologies used in Altera CPLDs. It also describes the segmented channel routing interconnect architecture used in Actel FPGAs and the LCA architecture used in Xilinx FPGAs.
The document presents an efficient FPGA implementation of convolution that reduces processing time using hardware computing. It implements the discrete linear convolution of two finite length sequences. The existing system uses DSP processors that consume more power and require more chip area with low speed. The proposed system implements convolution using VLSI architecture, consuming less power and requiring less chip area with high speed. It also works for signed and unsigned numbers and reduces processing time.
Field programmable gate arrays (FPGAs) are integrated circuits that can be configured by the customer or designer after manufacturing. FPGAs contain programmable logic components called logic blocks and a hierarchical interconnect that allows the blocks to be 'wired together' as per the design. The document discusses the basic FPGA architecture including logic blocks, interconnects and I/O blocks. It also explains the different FPGA families and programming technologies like SRAM, antifuse and EPROM/EEPROM. The Xilinx FPGA development flow and tools like ISE and its components are explained.
This document summarizes a student's MASc research on developing an area-efficient FPGA architecture for datapath circuits. It proposes combining bus-based and bit-based routing to better utilize multibit computing elements. Simulation results show the multi-bit logic block approach reduces routing area by 14% compared to conventional FPGAs. Future work involves exploring directional single-driver wires which could further reduce area by 25% and delay by 9% on average. The student seeks feedback on modifications to the CAD flow needed to support the new architectural features.
The document is a seminar report on FPGA technology in outer space applications. It discusses the history and evolution of FPGA technology over time, including increasing gate densities and falling prices. It describes typical FPGA architecture which includes configurable logic blocks, interconnects, and I/O pads. Modern FPGAs integrate additional resources like memory blocks, DSP slices, and soft processor cores. The document highlights applications of FPGAs in aerospace, including COTS boards and development kits. It also outlines future potential for FPGAs in more complex roles in space systems.
An FPGA is a programmable logic device containing an array of configurable logic blocks and interconnects that can be programmed to perform different logic functions. It allows reprogramming to perform different functions in microseconds. The key parts of an FPGA are I/O blocks around the edge to interface with other components, logic blocks in the interior to implement logic functions, and interconnects to connect the blocks. FPGAs are programmed by configuring electronic switches to define logic functions and connect the blocks as required.
The document discusses implementing convolution on an FPGA. It begins by introducing convolution and its applications in image processing. It then discusses the scope and technical approach of implementing discrete linear convolution on FPGA kits in order to perform convolution on images in real-time. The document outlines the structure of FPGAs, including configurable logic blocks and wiring tracks. It also discusses software requirements and provides an organization plan for subsequent chapters on linear convolution, FPGA technology, and a literature survey.
FPGA stands for Field Programmable Gate Array. It allows designers to change their designs late in the development cycle or even after deployment through field upgrades. An FPGA consists of Configurable Logic Blocks (CLBs) containing look-up tables, flip-flops, and logic functions. It also includes interconnect routing resources and I/O blocks. Memory blocks and clock management resources are integrated into the FPGA to support a wide range of applications across many industries.
This document summarizes the Domestic Violence Act of 2005 in India. It defines domestic violence, outlines the various forms it can take including physical, sexual, verbal, emotional, and economic abuse. It notes that women represent 95% of victims. The act aims to protect women from domestic violence and provides civil remedies like protection orders and maintenance orders. It recognizes the right of women to reside in the shared household and seek help from agencies like protection officers or service providers.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This document provides an introduction to FPGA design fundamentals including:
- Programmable logic devices like PLDs, CPLDs, and FPGAs which allow for reconfigurable logic circuits.
- The basic architecture of FPGAs including configurable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect structure.
- Verilog and VHDL as common hardware description languages used for FPGA design entry and simulation.
- A simple example of designing a half-adder circuit in VHDL, including entity, architecture, and behavioral modeling style.
This document summarizes a seminar on FPGA, CPLD, and VHDL programming basics. The seminar schedule includes sessions on FPGA technologies compared to previous programmable devices like CPLD, Microsemi FPGA devices and VHDL introduction. There is also an application example of using an FPGA for an Ethernet bus interface board and a discussion of current trends and technologies.
This document discusses FPGAs and their low power techniques. It begins with a brief history of programmable logic devices including PROMs, PLAs, and PALs which were the precursors to FPGAs. FPGA advantages are their reprogrammability, faster design times, and ability to fix designs by reprogramming compared to ASICs. The document then covers FPGA architecture including logic blocks, interconnects, and different routing architectures from vendors. Programming techniques like SRAM, antifuse, and floating gate are described. Low power design is an important aspect for FPGAs. The semiconductor industry is moving towards 3D FinFET transistors which allow for lower power and higher densities than planar transistors.
The document discusses the architecture of CPLDs and FPGAs. It begins by explaining the problems with using basic logic gates on PCBs and introduces programmable logic devices as a solution. It then describes different types of PLDs including PLA, PAL, GAL, CPLD and FPGA. CPLDs have a complexity between FPGAs and basic PLDs, containing non-volatile memory and supporting larger logic than PLDs. FPGAs contain logic cells, interconnects, and can implement thousands of gates. The document provides examples of implementing logic with different PLDs and describes the architecture and programming of CPLDs and FPGAs.
This document discusses Field Programmable Gate Arrays (FPGAs), including their history, components, applications, and advantages. FPGAs allow logic functions to be programmed in the field after manufacturing and consist of configurable logic blocks, input/output blocks, and a routing matrix. They are used widely in embedded systems, consumer electronics, communications, and more due to their flexibility, short development times, and ability to be updated in the field. FPGAs provide advantages over traditional ICs like long-term availability, field updates/upgrades, extremely short time to market, and massively parallel processing capabilities.
Programmable logic devices (PLD) like PALs, PLAs, GALs and CPLDs allow complex digital logic designs to be implemented in a single device. Newer devices like FPGAs can implement thousands of logic gates, supporting more complex designs than simpler PLDs which are limited to hundreds of gates. FPGAs contain an array of configurable logic blocks and interconnects that can be programmed by the user to realize different logic functions. CPLDs have a complexity between basic PLDs and FPGAs, including non-volatile configuration memory and supporting more complicated feedback paths than PLDs.
This document discusses programmable logic devices (PLD) including their purpose, types, and structure. The main types of PLDs are SPLDs (simple PLDs like ROM, PLA, PAL, GAL), CPLDs (complex PLDs), and FPGAs (field-programmable gate arrays). SPLDs have an input connection matrix connecting inputs to AND gates and an output connection matrix connecting AND gates to OR gates. CPLDs and FPGAs can implement more complex designs than SPLDs and support thousands of gates versus hundreds for SPLDs. FPGAs contain many identical logic cells that can be programmed to implement different functions.
FPGAs were introduced in 1984 as a programmable alternative to PLDs. They fill the gap between discrete logic and smaller PLDs on the low end and more expensive ASICs on the high end. The basic elements of an FPGA are configurable logic blocks (CLBs), configurable I/O blocks (IOBs), and a programmable interconnect. FPGAs from vendors like Xilinx and Altera have a regular architecture of CLBs surrounded by IOBs and connected via a hierarchy of programmable interconnects.
Automatic generation of platform architectures using open cl and fpga roadmapManolis Vavalis
This document discusses using OpenCL to automatically generate platform architectures for FPGAs. It introduces FPGAs and their architecture, then discusses how OpenCL can be used as a hardware description language. The Silicon OpenCL (SOpenCL) tool flow is presented, which takes an unmodified OpenCL application and converts it into an FPGA system design with hardware and software components. Key steps in SOpenCL include code transformations, granularity management, and architectural synthesis to generate customized FPGA accelerators from OpenCL kernels. Monte Carlo simulations are provided as an example of an application that could exploit multiple levels of parallelism on FPGAs using this approach.
This document presents a summary of a presentation on applying FPGAs for motor speed control. It was delivered by five students from the Electrical Engineering department at the University College of Engineering in Rajasthan, India. The presentation covered FPGA introductions, applications, structures, programming, and using an FPGA with an intelligent power module and motor to observe waveforms for motor speed control. It concluded that FPGAs provide flexibility for prototyping and application in areas like automotive, consumer electronics, and industrial controls.
The document provides an overview of field-programmable logic devices (FPLDs) such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). It discusses the history and basic architecture of CPLDs, including logic array blocks (LABs) and programmable interconnect arrays (PIAs). It also covers specific CPLD families and devices from vendors like Xilinx and Altera.
This document discusses system designing and modeling using field programmable gate arrays (FPGAs). It provides an overview of FPGA architecture, including logic blocks, interconnects, switch boxes, and input/output pads. Programming FPGAs involves using a hardware description language (HDL) like VHDL or Verilog to define the design, which is then synthesized, placed, and routed to the FPGA. Common applications of FPGAs include digital signal processing, image processing, cryptography, and ASIC prototyping. The document provides examples of FPGA components and programming.
The document discusses different types of programmable logic devices including CPLDs and FPGAs. It provides details on the architecture and workings of the Xilinx XC9500 CPLD family and Xilinx XC4000 FPGA family. The XC9500 CPLD uses function blocks containing macrocells with programmable AND and OR arrays. The XC4000 FPGA uses configurable logic blocks containing function generators, flip-flops and programmable multiplexers to implement logic functions. Both devices use programmable interconnects to route signals between blocks.
An FPGA is described as a reconfigurable integrated circuit containing an array of logic blocks and programmable interconnects. The document discusses an FPGA's architecture, including configurable logic blocks and routing resources. It also provides VHDL code for an 8-bit ALU implementation on an FPGA, including a process to handle data display on an LCD screen.
FPGA, VLSI design flow using HDL, introduction to behavior, logic and physica...Rup Chowdhury
Field-Programmable Gate Arrays (FPGAs) and Very Large Scale Integration (VLSI) design play pivotal roles in the development of modern electronic systems, offering a flexible and efficient platform for implementing complex digital circuits. This description delves into the world of FPGA and VLSI design flow using Hardware Description Languages (HDL) and introduces the crucial concepts of behavior, logic, and physical synthesis.
FPGA Overview:
FPGAs are reconfigurable semiconductor devices that allow designers to implement custom digital circuits, making them ideal for prototyping, rapid development, and applications requiring flexibility. They consist of an array of programmable logic blocks, configurable interconnects, and memory elements, providing a versatile hardware platform.
VLSI Design Flow using HDL:
The VLSI design flow is a systematic process employed by engineers to design, implement, and verify integrated circuits. Hardware description languages, such as Verilog and VHDL, are essential components of this flow. These languages enable designers to express the functionality and structure of digital circuits in a human-readable and simulation-friendly manner.
The Field Programmable Gate Array (FPGA) industry is expanding both in market share and in innovation. The tailored FPGA features make them a better choice to include FPGA in an increasing number of applications in the upcoming years. A constant development of FPGA technology has led to minimize the gap of performance levels between FPGA and Application Specific Integrated Circuit (ASIC). Hence, in recent years, FPGA based platforms are proven more attractive than ASICs since their performance is high in addition to the low cost of the development process and short time to market. Therefore, nowadays, FPGA is highly attractive for a huge range of applications in communications, computing, avionics, security, automotive and consumer electronics. Field Programmable Gate Array industry has shown a steady growth with a market prediction value of USD 9 billion by 2023. Currently, the FPGA companies started growing in reserch areas such as Artifitial Intelligence (AI), Internet of Thing (IoT) and LIght Detection and Ranging (LIDAR). The aim of this paper is to review the developments in FPGA.
This document discusses different types of programmable logic devices (PLDs), including simple PLDs (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). SPLDs can replace simple logic functions, while CPLDs can replace more complex functions equivalent to 2-64 SPLDs. FPGAs have the largest capacity and consist of configurable logic blocks and programmable interconnects. PLDs offer advantages over fixed logic devices like lower costs, faster design changes, and easier troubleshooting. The document provides examples and diagrams of PLD components like PALs, PLAs, and FPGA architectures.
This document discusses field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). It begins with an introduction to programmable logic technology and compares application specific integrated circuits, programmable logic devices, FPGAs, and CPLDs. Key differences between FPGAs and CPLDs are that FPGAs contain over 100,000 logic blocks while CPLDs typically contain thousands of logic gates. FPGAs also offer higher complexity and can implement high-grade data processing, while CPLDs offer moderate data processing. The document then discusses FPGA and CPLD families, performance, and technical development differences compared to microcontrollers. It provides block diagrams of C
Iaetsd a design of fpga with ledr encoding andIaetsd Iaetsd
This document proposes two techniques for reducing power consumption in asynchronous FPGAs: 1) Fine grain power gating which allows individual lookup tables to power gate independently, putting inactive tables to sleep. 2) Using level encoding dual rail (LEDR) architecture for data encoding which reduces dynamic power compared to existing dual rail encoding by eliminating the need for spacers between data values. Simulation results show the proposed FPGA design consuming 7mW of power which is reduced compared to non power gating approaches.
Programmable logic controller performance enhancement by field programmable g...ISA Interchange
This document proposes designing a programmable logic controller (PLC) using a field programmable gate array (FPGA) to improve performance. The FPGA implementation allows for parallel execution of logic compared to a typical microprocessor-based PLC. A GUI is developed in Visual Basic to program ladder logic into the FPGA by transmitting hex codes representing the logic. The proposed design architecture includes 4 rungs that can each contain up to 16 components. Simulation results demonstrate the FPGA-based PLC functioning for typical logic and alarm applications.
Programmable logic controller performance enhancement by field programmable g...
Programmable Devices En 01
1. October 2005
October 2008
October 2012
“FPGA – CPLD Technologies
and VHDL programming basics”
Seminar
Updated 2012 Version
Teodoro BOVE (Alstom) - Svetozar Jovanovic (Altran-
Italia)
2. Programmable logic and VHDL
programming
SEMINAR SCHEDULE
l 09.00-09.15 Welcome and coffee
l 09.15-10.30 FPGA Technologies compared to previous
generation of programmable devices like SPLD e
CPLD
l 10.30-10.45 Coffee Break
l 10.45-13.00 Today FPGA scenario and ACTEL® PROAsic® APA
devices family » for LO.RE railway vehicle
RACK-BUS
l 13.00-13.45 Lunch Break
l 13.45-15.00 Introduction to VHDL programming
l 15.00-15.30 Coffee Break
l 15.30-17.00 Application example: FPGA for ETHERNET BUS
interface board LO.RE
l 17.00-17.30 Today trands and last news- technology evolution
Date of last change Reference/Name of Presentation/SN 2
3. FPGA technologies comparison to previous
generation programmable devices SPLD
and CPLD / history overview
27-12-2008 FPGA-CPLD-VHDL Seminar 3
5. CPLD e FPGA configuration
bitstreaming
The configuration operations of programmable devices is implemented
switching stably the connection transistors, nowtimes the typical
technologies are EEPROM, SRAM, FLASH, mainly through ISP (in circuit
programming feature) and ANTIFUSE which is one time not-reversible
configuration. The user logic cells of course are all in x-CMOS tech.
27-12-2008 FPGA-CPLD-VHDL Seminar 5
6. CPLD ARCHITECTURE
The CPLD architecture for example is as follows:
Picture 8: PIA -Programmable interconnect array
Picture 13: Global routing pool
27-12-2008 FPGA-CPLD-VHDL Seminar 6
8. CPLD global aspects
• The internal signals propagation time are predictable because the routing paths
are all the same for all logic macrocells. Normally the typical delays are between
4 and 15 ns IN-OUT
• The typical CPLD architecture is based on more macrocelles connected between
them. Each macrocell is implemented with more integrated basic logic gates builded
toghether, like happens in PLA/PAL SPLD (22V10 like) devices. All the macrocells
are interconnected between them with a dedicated logic matrix
• The CPLD common architecture is’ « typically not so much flexible », this on the
other hand is also a their advantage because the internal signal delays are
predictable :
• The CPLD devices are « right tailored » for a some typical applications
• The « LOGIC » volume of these devices is up-limited to 75K Gate
• The typical applications are for instance various kind of « low level »
interfaces, like BUS control signals, simple state machine, simple real time
processing in applications without memory requirements, combinatorial
functions
27-12-2008 FPGA-CPLD-VHDL Seminar 8
9. Current FPGA-CPLD scenario and comparison
between the FPGA ACTEL® PROASIC PLUS
« APA « LO.RE project choice and competitor
devices
27-12-2008 FPGA-CPLD-VHDL Seminar 9
10. FPGA ARCHITECTURE
This picture shows an example:
27-12-2008 FPGA-CPLD-VHDL Seminar 10
12. Current FPGA overview
Has been considered three FPGA devices providers /
vendors:
• XILINX®
• ALTERA®
• ACTEL®
Some others was not considered only for practical
reasons.
Each one (independently by economical aspects) has its
preferred market, is also true that they has different
device architectural approach. This has the consequence
that logic implementations are different.
27-12-2008 FPGA-CPLD-VHDL Seminar 12
13. XILINX®, ALTERA®, ACTEL®
All the mentioned FPGA providers are using different
physical implementations (both architectural and
technological) this means that same VHDL designs could
produce better or less kind of performances.
Specially what has a relevant impact on the overall FPGA
performances, is the « connectivity capability» between its
logic elements and the mean delay amount.
This is resulting in :
• timing performances
• logic, routing and I/O resources saturation
27-12-2008 FPGA-CPLD-VHDL Seminar 13
14. ALTERA® typical architecture
This architecture is characterised by following morphoology :
Altera : The LE logic elements are all grouped in the logic array blocks,
for instance 8 or 16 with great connectivity between the macrocells which
belongs to the same LE, the connectivity between different groups is
demanded to relatively limited « cross highways » as shown below (this
because certain amount of silicon area is filled by group of LE itself) :
27-12-2008 FPGA-CPLD-VHDL Seminar 14
15. XILINX® typical architecture
With a different approach, Xilinx prefer single LE, simplest macrocells
blocks interconnected with a diffentiated stronger net, as shown below,
which gives a very good connectivity and routing capability, the direct
consequence is a benefit role in minimizing signals delay:
27-12-2008 FPGA-CPLD-VHDL Seminar 15
16. ACTEL® typical architecture
The Actel architecture approach follows the Xilinix « direction », but much
more intensively :
In practice the ACTEL® FPGA devices achieve a « granularity » up to a
« quasi » ASIC level. The LE logic elements are simple, but with really
impressive connectivity and routing capability between them, this imply a
valuable benefit in terms of signals delay as shown below:
27-12-2008 FPGA-CPLD-VHDL Seminar 16
17. Comparison about architecture approaches
- ALTERA® devices architecture is typically aggregating LE the logic
elements, in other words blocks of macrocells, the consequence is that
are favored designs with highly concentrated logic and / or
combinatorial complexity, on the other hand this approach may impact
a global connectivity, and IN-OUT signal delay
- XILINIX® devices architecture has a different approach, in practice, the
major difference are:
• Less aggregation of simplest LE logic elements
• More resources dedicated to the connectivity and routing between LE.
This may affect designs, the complexity is distributed over more LE, which
are anyway connectable due to rich and differentiated routing resources.
- ACTEL® devices as already mentioned about the logic elements LE
they are the simplest compared to other two, this results in a high grade
of “granularity”, the connectivity and routing resources are powerful and
flexible, so these devices are ASIC like. The impact on designs is a large
“spectrum” of implementable applications, high device usage efficiency.
The other side of “medal” is that global application speed is limited.
27-12-2008 FPGA-CPLD-VHDL Seminar 17
18. Comparing table for the LO.RE
project
2005 FPGA COMPARE I/O I/O SPEED DEVELOPING QUOT. POWER
PACK. TEC. VOLTAGE. PROG. COMMENTS
TABLE FOR LORE PROJ. PINS NEC GRADE SYSTEM CONS.
208 GOOD ISE WEB / ISP EFFICiENT
XILINIX SPARTAN 3 PQFP 141 DESKTOP 20$ + 3: 1.2V EXTERNAL ARCHITECTURE, HIGH
VOLAT.
XC3S200 173 MAX LIMITED FLASH 2.6V FLASH O R MEDIUM SPEED, MEDIUM
SRAM
200KG 256 173 CLKIN MODELSIM PROG 3.4V PROM VIA COMPLEXITY LOGIC
FBGA 280 MHZ 500$ JTAG ELEMENTS
NEXT GEN. DEVICE MORE I/O 190 IN FBGA PACK, MAY BE INTERNAL SMALL INTERNAL FLASH
XC3S500E
DUE TO FLASH TECH.
LIBERO IDE, VERY HIGH RELIABILITY
208 SUFFIC. SYNPLIFY, ISP ONE IN HARSH
ACTEL PROASIC PLUS
PQFP SYNTH, NON- TIME ENVIRONMENT HIGH
APA 150 158 2: 2.5V VERY
173 MAX SIMULATORE 25$ VOLAT. PROGRAM GRANULARITY
150KG 186 3.3V LOW
256 CLKIN MODELSIM FLASH MING VIA ARCHITECTURE ,
FBGA 180 MHZ VHDL JTAG SIMPLE LOGIC CELLS,
FREE OF RICH ROUTING
CHARGE RESOURCES
NEXT GEN. DEVICE REDUCED PROGRAMMING TIME 1 MIN. TO TEN SE. SMALL INTERNAL FLASH
A3P400
VERY QUARTUS COMPLEX
240 GOOD TWO ISP ARCHITECTURE, HIGH
PQFP LIMITED 27$ + EXTERNAL INTEGRATION LE
ALTERA CYCLONE EP1C6 173 VOLAT. 2: 1.5V RELAT.
173 MAX EDITION FREE FLASH FLASH O R ELEMENTS, WELL
300KG 185 CLKIN SRAM 3.3V HIGH
256 OR FULL WITH PROG PROM VIA SUITED FOR COMPLEX
FBGA 400 MHZ MODELSIM 2000 JTAG AND FAST
$ APPLICATIONS
NEXT GEN. DEVICE BETTER INTEGRATION ADDED DSP FUNCTIONS, ENHANCED POWER CONSUMPTION
EP2C6
27-12-2008 FPGA-CPLD-VHDL Seminar 18
19. ACTEL® PROAsic PLUS® APA
FPGA – Choice highlights:
• For LO.RE project the choice has been finalised, resulting in ACTEL®
FPGA APA150 device, considering the following aspects:
• Higher I/O pin count, 186 in FBGA package – (183 used pin)
• Properly tailored gate volume (150 Kgate)
• Two operating voltages 2.5 V for core and 3.3 V for the I/O
• Free of charge « LIBERO® » developing system Modelsim® included
• Very low power consumption
• No need external device for data retention
• High reliability in hostile and harsh environment
• Easy technical support, very well suited in Italy
• Overall Logic elements architecture, well calibrated to the application
27-12-2008 FPGA-CPLD-VHDL Seminar 19
20. FPGA-CPLD global aspects
and conclusions A
Looking back on previous considerations, comparing FPGA vs. CPLD we
can state that:
• The FPGA’s has shown generally speaking improved average density,
and complexity, possibly driven by growing design integration demand of
embedded SRAM memory, FLASH memory, processor cores, this isn’t
case for CPLD
• Nowtimes the FPGA devices are reaching 3,5 million gates
• As « pro » for the CPLD, still the predictable signals delay is an
advantage, that’s also one of the reasons because this devices has still
their market
• The case of FPGA’s is that there is still a unpredictability of signal
delays, but the enormous gate avalaibility and connectivity and routing
resources are partially compensating this aspect.
27-12-2008 FPGA-CPLD-VHDL Seminar 20
21. FPGA-CPLD global aspects and
conclusions B
• About the EDA tools is interesting to observe that today a place and
route process for a FPGA 1 MLN gate big, used at 90% and with the
95% fixed I/O, takes on a modern laptop something like 15 mins
• In 1993 a FPGA 5K gate big used at 60% and 85% fixed I/O has been
taking several hours to complete the place and route process, with
1 to 15 net left to be connected manually
• So the EDA tools has been following in some way interleaved the
technology in FPGA development and design, even that, today you can
find in a current design pin to pin delays form 10 to 40 ns, this because
the FPGA architectures has been improved but are still too much
dependent from the origins
• Today in the CPLD usage is still possible to obtain pin to pin delays
contained in 5-15 ns range
• For the reasons above, nowtimes in the FPGA are integrating dedicate
I/O channels for high or very high frequency signals, for instance the
standard JEDEC LVPECL signals, differential, LVDS or similar etc.
27-12-2008 FPGA-CPLD-VHDL Seminar 21
22. FPGA-CPLD global aspects and
conclusions C
• Today the FPGA thanks also to HW languages VHDL,VERILOG,
SYSTEM VERILOG are integrating as already mentioned above, variuous
IP, embedded 16/32 bit processors realizing systems on chip « SoC »,
which are replacing sometimes a entaire HW boards belonging times ago
• In conclusion we can say that FPGA and CPLD are not in competition at
all, each one has its market
• The very well known differences, are sharply separating their usage in
applications. Very often in the same application you can find both FPGA
and CPLD which are satisfying well different requirements:
- FPGA for medium-high end designs
- CPLD for low end designs, or special cases
27-12-2008 FPGA-CPLD-VHDL Seminar 22
23. VHDL programming basics
Each slide will be explained using also a simulation
examples with « ACTIVE® VHDL » EDA tool
27-12-2008 FPGA-CPLD-VHDL Seminar 23
24. Preface VHDL 93 (what is this ?)
• Is a digital HW programming language (as VERILOG or SYS. VERILOG)
• Is a IEEE standard IEEE®, the 93 is last version
• Can be considered in some way higher level abstraction language
compared to VERILOG
• Is a parallel language, sometimes include sequential statements « C » like
• The implementation statements can be inferred, or instantiated (see the
following section « VHDL comments « A »)
• The designs implemented as inferred pure VHDL source code, are portable
over all HW platforms FPGA – CPLD in a vendor independent way
• The designs implemented with instantiated statments are using vendor
specific HDL macros, therefore are depending by them
• Today there are a lot IP HDL open source or to pay as a package or netlist
• In the following sections (see « Template VHDL ») you can see code
examples
27-12-2008 FPGA-CPLD-VHDL Seminar 24
25. Comments on VHDL section « A »
• Is useful to clear a bit the concepts of INFRERENCE and INSTANTCE
what they are in practice ? :
• INSTANCE – is to insert in your VHDL code a statement which is
referring to a « component » which is a separate file that contain a
blind VHDL code, the statement in your code is « viewing » only the
components inputs and outputs, that are usable in your code to
interact with a component itself. The component usually is vendor
own property. So very often in its EDA tools editions the vendors
leave available for free a basic digital components, like counters,
arithmetic functions, glue logic, logic functions etc. Of course its
usage is very convenient because you don’t have to write the code
for them, but your design is depending by specific HW platform
• INFERENCE – see the next page
27-12-2008 FPGA-CPLD-VHDL Seminar 25
26. Comments on VHDL section « A »
continued
• INFERENCE – means to write the VHDL code using the
language primitives and instructions – key words, this is almost
mandatory to complete whole design, because even you are
using also a vendor components, then anyway you have to write
the VHDL code to interface – intergrate it in your design.
Is straightforward that you can write also your open source VHDL
components and use it in your design. This approach has the
advantage that your code ideally is portable on every HW
platform regardless the vendor that you want to use
27-12-2008 FPGA-CPLD-VHDL Seminar 26
28. Comments on VHDL section « B »
• A very important concept is that every VHDL complete design (that
has to be fit in a physical programmable device) is normally
hierarchically organized. So the typical structure of a VHDL deign is a
kind of « tree » of different files (extension *.vhd) :
- top entity VHDL (device I/O visibility)
- component 1 VHDL
entity of component 1
- component 1a VHDL
entity of component 1a
- component 2 VHDL
entity of component 2
- component 2a VHDL
entity of component 2a
The top entity VHDL is contained in a VHDL main file, on which
appears as language structure which include all the I/O of device
signals name, every one of them has its reference inside the main file-
27-12-2008 FPGA-CPLD-VHDL Seminar 28
29. Comments on VHDL section « B »
continued
some of them have a reference to a sections limited at main file,
others are « pointing » to one or more components, as shown in
hierarchy tree shown above, in previous page.
Another important aspect to highlight is the VHDL design testing.
The VHDL testing is in pratice a simulation done with proper EDA
tools. For instance two very popular EDA simulators are
Moedlsim® and ACTIVE®. The simulation can be done at
different level of programmable device design:
1) functional simulation, at VHDL code entry level
2) postsynthesis simulation at physical implementation level
(see for instance a SYNPLIFY® synthsizer)
3) postlayout simulation after the place and route succesful
process
For more details see the examples that follows-
27-12-2008 FPGA-CPLD-VHDL Seminar 29
30. Comments on VHDL section « B »
continued
As global knowledge, has to be pointed out, that every
type of simulation is done « facing » two objects:
- the whole VHDL design under test, with file that contains the
« top entity »
- the « testbench VHDL file » that contains also the top entity
which is the « mirror » of VHDL design top entity. This file inlude
all the statements that are stimulating top entity inputs
The simulation EDA tool, « reads » both, merging properly the related
signals, achieving the design under test outputs time evolving view,
giving to user the opportunity to evaluate the signals behaviour.
Follows the VHDL section « C », VHDL project design flow chart and
project example.
27-12-2008 FPGA-CPLD-VHDL Seminar 30
31. Comments on VHDL section « C »
Here are shown some examples of VHDL language primitives
and defines, assignements:
Constants : constant NAME := integer 1000;
Variables : signal, std_logic, std_logic_vector(n..0) for 1 or
more bit, integer
Control : if, then, else, elsif, endif, when-case, when
others (like default in C), for, while
Assignement : SWAP <= dir_cross; var <= ‘0’;
Combinatorial : and, or, nand, not, xor etc.
Comparing : = equal
Rising clk edge capture : if (clock’event) and (clock=‘1’)
27-12-2008 FPGA-CPLD-VHDL Seminar 31
32. VHDL design process Flow chart
ACTIVE VHDL FPGA DESIGN
VHDL TOOL PROCESS LIBERO ACTEL INTEGRATED TOOL
SYTHESIS AND PHYSICAL
W AVEFORM SHAPING MAPPING, VHDL
TRANSLATION IN NETLIST PLACE AND ROUTE
BLOCK DIAGRAM
.EDN FILE
SYNPLIFY TOOL
BACKANNOTATION
VHDL DESIGN ENTRY PROCESS (VHDL
WARNING AND TIMING EXTRACTION)
CHECK-OUT
IF NECESSARY DESIGNER
SYNTAX FIRST CHECK CONSTRAINT INJECTION,
(FORMAL COMPILE) FLOORPLANNING
POSTSYNTHESIS
OPTIMISATION
SIMULATION
TESTBENCH SIMULATION POSTLAYOUT TIMING
STIMULUS SYNTHESIS ANALYSIS
DESIGNER PROCESSING
POSTLAYOUT
FUNCTIONAL SIMULATION
CONSTRAINTS ENTRY SIMULATION
BITSTREAM STAPL FILE
COMPILE
GENERATION
FIRST
EXAMPLE
END SECOND
FPGA PROGRAMMING EXAMPLE
END
27-12-2008 FPGA-CPLD-VHDL Seminar 32
33. A VHDL design project example
l Project concept and wanted signals time evolution
l Functional block diagram
l VHDL code design
l Testbench stimuli signal definitions
l VHDL functional simulation
l The VHDL entry and simulation has been done with EDA
ACTIVE® VHDL tool
27-12-2008 FPGA-CPLD-VHDL Seminar 33
34. Functional block diagram (for the
other signals, the logic is the same)
BUS SIGNAL GENERATOR
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
CLK
SET OUT BUS WR
RESET
SET OUT BUS ALE
RESET
WR
ALE
27-12-2008 FPGA-CPLD-VHDL Seminar 34
46. Application example: Project- VHDL design for a
FPGA part of ETHERNET CONNECTIVITY board
Each slide will be explained using also a design- simulation
examples with « ACTEL® Libero® » EDA tool
27-12-2008 FPGA-CPLD-VHDL Seminar 46
47. Board block diagram and FPGA
interfacing
C
EEPROM GPIO TEST POINTS A
SPI INTERF E LED E 232 N
CAN PHYSICAL DRIVER
C
O
VOLTAGE N
MONITOR D SP TMS320F2812 16 BIT ADDR_DSP
N
AND RESET
SECTION
JTAG / ICE
RS232
16 BIT ADDR_DSP
16 BIT DATA_DSP CONN
16 BIT DATA_DSP
CTR_DSP
SM SC LAN 91C111 T
R R J45
C A AND
CLK
M AC + PHY
O
N
B
SECTION F LED
U O
N CTR_DSP_C LAN
F
E OSC OR ETH ER NET
F
C BUFFERED
E C ONTROLLER
T DESKEW ED
R
O LORE CLK
S CTR_DX
R
S OSC
L S
E
T R
V
O
E A
L ADDR_DX
L M
O 5 GENERAL PURPOSE CONNECTIONS TO LORE
S
R
H
E
I PARI POW ER SUPPLY
F FPGA BU S_SW ITC HER 16 BIT DATA_DX
B
T CTR_LORE SEC TION
E
U
R
S ADDR_LORE 16 BIT
S +5V
B
+5
CTR_SX +3.3V
A S
C
+2.5V
T DATA_LORE 16 BIT
K
O
R
P A
L
+3,3 ISP ADDR_SX M
A
V PROGRAM M ING
N
E
M INIFLAT CONN IL +5V ARRIVA
DISPA RI +5V D AL BUS
16 BIT DATA_SX LORE
27-12-2008 FPGA-CPLD-VHDL Seminar 47
48. Board and FPGA brief
functional explanation
In this application the FPGA has been set to be a interface a
ETHERNET 10/100 Mbit for the “LORE” custom BUS,
toghther with a DSP and LAN controller chip.
The interface between the DSP and custom rack BUS
backplane has been implemented through a double external
SRAM buffer, configured in a “ping-pong” way.
One of the main reasons for doubled SRAM implementation
was to achieve a continous upstream and downstream data
between DSP on the ETHERNET board and the RACK CPU.
For example in downsteram process, the FPGA was
charghed to take care that during the DSP writes in one of
two SRAM, the RACK CPU was addressed to read from the
other one SRAM. So the main FPGA function was to manage
the handshake between the CPU and DSP, switching
properly the data flowing through the SRAM double buffer.
The following block diagram shows this: --
27-12-2008 FPGA-CPLD-VHDL Seminar 48
49. BUS switch block diagram,
rack LO.RE CPU—DSP via FPGA
27-12-2008 FPGA-CPLD-VHDL Seminar 49
50. Switch BUS handshake
testbench sequence
Date of last change Reference/Name of Presentation/SN 50
51. FPGA has been designed in fully
integrated ACTEL tool « LIBERO »
27-12-2008 FPGA-CPLD-VHDL Seminar 51
52. Below is shown the VHDL top
entity in peripheral.vhd file
27-12-2008 FPGA-CPLD-VHDL Seminar 52
67. Conclusions A
Today seminar had a goal to give a simple « window » to a programmable
logic devices, alligned with state of art in this electronics field.
Another objective was to introduce not experienced people to the HW
programming, as example has been used the VHDL 93 language.
Has been focused the VHDL highlight aspects, trying to give a real feeling
with the « core » of code logic and developing.
The main issues related to that was to point out :
- advantage to have a portable HW language:
for instance if one write a code for a special custom logic function
component in inferenced way, according to a basic HW platform
requirement, is possible to use it on a FPGA or even on an CPLD
- the simulation, using VHDL is possible to create a virtually
whatever complexity stimulus
à
27-12-2008 FPGA-CPLD-VHDL Seminar 67
68. Conclusions B
Nowtimes the EDA tools has achieved very powerful performances, offering
to a designers – architects, integrated suites to develop the whole digital
implementation on a programmable chip, from CPLD to complex FPGA’s .
Today are also available a lot of IP’s free or to pay, which make easy its
integration in a design. The last trend is going towards to integrate also a
various processors cores, pushing the integration of programmable devices
at reasonable prices and high performances.
One example is ALTERA® vendor, which has its « QUARTUS 2® » EDA
which include several free IP, macros and the NIOS 2® 32 bit RISC
processor. In that EDA is included a wizard guided tool « SOPC BUILDER »
which is powerful graphical-to-VHDL generator. With this tool is relatively
easy to build-up a single or multiprocessor platform mixed with rich library of
IP’s and macros (UART, SPI, GPIO etc.). The tool is easy interacting with a
NIOS EDA®, which is a developing, debug platform for C/C++ code which
will run on a NIOS 2® processors, from this EDA you can write a code and
then simulate it with Modelsim® running the code on NIOS 2 together with
its peripherals.
27-12-2008 FPGA-CPLD-VHDL Seminar 68
69. Conclusions C
The purpose of this seminar – presentation was
not intended to approach a comparison between
ASIC and/or programmable devices, even now is
also possible to develop on a programmable
device entaire application and do the “hardcopy”
on a silicon getting a wanted ASIC tested chip.
Even what sentenced above, is clear that in some
way the end performances “distance” between a
programmable devices and ASICs, today is not so
big as in relatively past times.
27-12-2008 FPGA-CPLD-VHDL Seminar 69